DRV104PWPR Datasheet, PDF (13/25 Pages) Texas Instruments – 1.2A PWM High-Side Driver

BYPASSING
A 1µF ceramic bypass capacitor is adequate for uniform duty
cycle control when switching loads of less than 0.5A. Larger
bypass capacitors are required when switching high-current
loads. A 10µF ceramic capacitor is recommended for heavy-
duty (1.2A) applications. It may also be desirable to run the
DRV104 and load driver on separate power supplies at high-
load currents. Bypassing is especially critical near the abso-
lute maximum supply voltage of 32V. In the event of a current
overload, the DRV104 current limit responds in microsec-
onds, dropping the load current to zero. With inadequate
bypassing, energy stored in the supply line inductance can
lift the supply sufficiently to exceed voltage breakdown with
catastrophic results.
Place the flyback diode at the DRV104 end when driving long
(inductive) cables to a remotely located load. This minimizes
RFI/EMI and helps protect the output DMOS transistor from
breakdown caused by dI/dt transients. Fast rectifier diodes
such as epitaxial silicon or Schottky types are recommended
for use as flyback diodes.
APPLICATIONS CIRCUITS
SINGLE AND MULTICHANNEL
The DRV104 can be used in a variety of ways with resistive
and inductive loads. As a single-channel driver, it can be
placed on one PC board or inside a solenoid, relay, actuator,
valve, motor, heater, thermoelectric cooler, or lamp housing.
In high-density systems, multichannel power drivers may be
packed close together on a PC board. For these switching
applications, it is important to provide power supply bypass-
ing as close to the driver IC as possible to avoid cross-
coupling of spikes from one circuit to another. Also, in some
applications, it may be necessary to keep beat frequencies
(sum and difference between DRV oscillators or between
DRV oscillators and system clock frequencies) from interfer-
ing with low-level analog circuits that are located relatively
near to the power drivers. Paralleling device outputs is not
recommended as unequal load sharing and device damage
will result.
BEAT FREQUENCIES IN NON-SYNCHRONIZED
MULTICHANNEL SYSTEMS
In many multichannel systems, beat frequencies are of no
consequence where each DRV uses its own internal oscilla-
tor.
Beat frequencies can be intentionally set up to be outside the
measurement base-band to avoid interference in sensitive
analog circuits located nearby. For example, with two
DRV104s, a beat frequency of 22.5kHz can be established
by setting one internal oscillator to a center of 62.5kHz and
the other to 40kHz. Considering the specification of ±20%
frequency accuracy, the beat could range from 2kHz (48kHz
and 50kHz) to 43kHz (75kHz and 32kHz). By limiting the
analog measurement bandwidth to 100Hz, for example,
interference can be avoided.
BEAT FREQUENCY ELIMINATION—OPTIONAL
SYNCHRONIZATION
The benefit of synchronization in multichannel systems is
that measurement interference can be avoided in low-level
analog circuits, particularly when physically close to the
DRVs. Specifically, synchronization will accomplish the fol-
lowing:
1. Eliminate beat frequencies between DRVs or DRVs and
the system clock.
2. Predict quiet or non-switching times.
Synchronization of DRV104s is possible by using one oscil-
lator frequency for all DRVs. See Figure 15 for an example
of one DRV internal oscillator as the master and the others
as slaves. Also, one external clock can be used as the
master and all the others as slaves.
PEAK SUPPLY CURRENT ELIMINATION—OPTIONAL
SWITCHING SKEW
In many systems, particularly where only a few channels are
used or low magnitude load currents are present, it is
unnecessary to skew the switching times.
In some multichannel systems, where just PWM is used,
without initial dc time delay, simultaneous switching of edges
can cause large peak currents to be drawn from the main
power supply. This is similar to that which occurs when
multiple switching power supplies draw current from one
power source.
Peak currents can be reduced by synchronizing oscillators
and skewing switching edges. Synchronization has the added
benefit of eliminating beat frequencies, as discussed above.
Skewing can be accomplished by using a polyphase clock
approach, which intentionally delays the time that each DRV
switches on PWM edges.
The DRV104 is useful for a variety of relay driver applications
(see Figures 16 and 17), as well as valve drivers (see Figures
18 and 19).
DRV104
13
SBVS036B
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