BQ2011K_11 Datasheet, PDF (13/22 Pages) Texas Instruments – Gas Gauge IC for High Discharge Rates

bq2011K
The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency fac-
tors are used. The time to change CR varies due to the
user-selectable count rates.
The discharge rate flags, DR2–0, are bits 6–4.
FLGS2 Bits
7
6
5
4
3210
-
DR2 DR1 DR0 - - -
They are used to determine the present discharge re-
gime as follows:
DR2
0
0
0
0
1
DR1
0
0
1
1
0
DR0
0
1
0
1
0
VSRO(mV)
0 < V_SRO ≤ 10
10 < V_SRO ≤ 20
20 < V_SRO ≤ 40
40 < V_SRO ≤ 60
V_SRO > 60
The overload flag (OVLD) is asserted when a discharge
overload is detected, VSRO > 60mV. OVLD remains as-
serted as long as the condition is valid.
FLGS2 Bits
7
65
4
3
2
-
--
-
-
-
1
0
- OVLD
Output Control Register (OCTL)
The write-only OCTL register (address=0ah) provides the
system with a means to check the display connections for
the bq2011K. The segment drivers may be overwritten by
data from OCTL when the least-significant bit of OCTL,
OCE, is set. The data in bits OC5–1 of the OCTL register
(see Table 5 for details) is output onto the segment pins,
SEG5–1, respectively if OCE=1. Whenever OCE is written
to 1, the MSB of OCTL should be set to a 1. The OCE reg-
ister location must be cleared to return the bq2011K to
normal operation. OCE may be cleared by either writing
the bit to a logic zero via the serial port or by resetting the
bq2011K as explained below. Note: Whenever the OCTL
register is written, the MSB of OCTL should be written to a
logic one.
Reset Register (RST)
The reset register (address=39h) provides the means to
perform a software-controlled reset of the device. A full
device reset may be accomplished by first writing LMD
(address = 05h) to 00h and then writing the RST regis-
ter contents from 00h to 80h. Setting any bit other than
the most-significant bit of the RST register is not al-
lowed, and results in improper operation of the
bq2011K.
Resetting the bq2011K sets the following:
I LMD = PFC
I VDQ, OCE, and NAC = 0
(NAC = PFC when PROG4 = L)
I BRP = 1
Display
The bq2011K can directly display capacity information
using low-power LEDs. If LEDs are used, the segment
pins should be tied to VCC, the battery, or the LCOM pin
through resistors for programming the bq2011K.
The bq2011K displays the battery charge state in abso-
lute mode. In absolute mode, each segment represents a
fixed amount of charge, based on the initial PFC. In ab-
solute mode, each segment represents 20% of the PFC.
As the battery wears out over time, it is possible for the
LMD to be below the initial PFC. In this case, all of the
LEDs may not turn on, representing the reduction in
the actual battery capacity.
The capacity display is also adjusted for the present bat-
tery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does not
affect the NAC register. The temperature adjustments are
detailed in the TMPGG register description.
When DISP is tied to VCC, the SEG1–5 outputs are inac-
tive. When DISP is left floating, the display becomes ac-
tive during charge if the NAC registers are counting at a
rate equivalent to VSRO < -2mV or fast discharge if the
NAC registers are counting at a rate equivalent to VSRO
> 2mV. When DISP is left floating, the display also be-
comes active after the detection of a discharge signal
with a minimum amplitude of VSR > 20mV (10A for RS =
0.002Ω) and a minimum pulse width of 25ms. When
DISP is pulled low, the segment outputs become active
for 4s, ± 0.5s.
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