AFE0064_14 Datasheet, PDF (13/32 Pages) Texas Instruments – 64 Channel Analog Front End for Digital X-Ray Detector

AFE0064
www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009
IRST
SHR
INTG
SHS
STI
CLK
EOC
t1
t9
t4
t3
t1
t2
Additional
133 clocks
t - Scan
t1
TFT ON (t5) _{~0.5 mSec}
t8
t6
WAIT
DATA READ
Figure 7. Device Operation at Higher Scan Times (sequential mode shown, however the same is possible
for simultaneous mode)
As shown in Figure 7, a data read can be started by issuing a STI pulse after SHS and well before IRST. In this
case the device goes into a ‘wait’ state after the data read is complete. The device remains in this wait state until
it receives IRST and STI rising edges. Note that the clock can be stopped (or kept running) in the wait state
however it is necessary to provide an additional 133 or 33 clocks after IRST falling edge depending on sequential
or simultaneous mode selection respectively. It is recommended to stop the clock after the device receives 133
or 33 clocks depending on mode selection until the next STI pulse. This helps to get maximum SNR from the
device. However it is allowed to use a free running clock.
Cascading Two AFE0064 Devices to Scan 128 Channels:
It is possible to cascade two AFE0064 devices to scan 128 channels. This feature is useful for sequential mode
and allows the use of a 4 channel, multiplexed input ADC for two AFEs.
In that case, STO of device 1 is connected to STI of device 2. Other control pins (INTG, IRTS, SHR, SHS, CLK)
of both devices are connected to each other.
As shown in figure 8, STO falling edge is delayed by one clock from STI falling edge. (STO falling edge aligns
with first clock falling edge.) Device 2 data out starts with the second clock rising edge (the first CLK rising edge
after STI falling edge for device 2). Effectively, data from the four output drivers of the two devices is presented
on every rising edge in the following sequence:
Clock 1,5,9...: OUT-1 of Device 1
Clock 2,6,10...: OUT-1 of Device 2
Clock 3,7,11...: OUT-0 of Device 1
Clock 4,8,12...: OUT-0 of Device 2
Note this output sequence when connecting a multiplexed input ADC at a device output.
Copyright © 2009, Texas Instruments Incorporated
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