ADS8505_14 Datasheet, PDF (13/27 Pages) Texas Instruments – 16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER

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R/C
BUSY
4.75V
VANA
VDIG
t_c
t_w1
t_pd
0 ns MIN
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
t_w1
t_pd
DATA BUS
Unknown
Hi-Z
Not Valid
Hi-Z
Figure 26. ADC Reset
Not Valid
Data Valid
t_d3
ADC RESET
The ADC reset function of the ADS8505 can be used to terminate the current conversion cycle. Bringing R/C low
for at least 40 ns while BUSY is low will initiate the ADC reset. To initiate a new conversion, R/C must return to
the high state and remain high long enough to acquire a new sample (see Table 3, t_c) before going low to initiate
the next conversion sequence. In applications that do not monitor the BUSY signal, it is recommended that the
ADC reset function be implemented as part of a system initialization sequence.
INPUT RANGES
The ADS8505 offers a standard ±10-V input range. Figure 28 shows the necessary circuit connections for the
ADS8505 with and without hardware trim. Offset and full-scale error specifications are tested and specified with
the fixed resistors shown in Figure 28(b). Full-scale error includes offset and gain errors measured at both +FS
and –FS. Adjustments for offset and gain are described in the CALIBRATION section of this data sheet.
Offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
CALIBRATION section).
The nominal input impedance of 11.5 kΩ results from the combination of the internal resistor network shown on
the front page of the product data sheet and the external resistors. The input resistor divider network provides
inherent overvoltage protection assured to at least ±25 V. The 1% resistors used for the external circuitry do not
compromise the accuracy or drift of the converter. They have little influence relative to the internal resistors, and
tighter tolerances are not required.
The input signal must be referenced to AGND1. This minimizes the ground loop problem typical to analog
designs. The analog signal should be driven by a low impedance source. A typical driving circuit using an
OPA627 or OPA132 is shown in Figure 27.
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