SM320C6748-HIREL Datasheet, PDF (128/266 Pages) Texas Instruments – SM320C6748-HIREL Fixed- and Floating-Point Digital Signal Processor

SM320C6748-HIREL
SPRS947 – JUNE 2016
www.ti.com
Table 4-59. Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V]⁽¹⁾⁽²⁾
(see Figure 4-35)
NO.
PARAMETER
1
t_d(CKSH-
CKRXH)
2
t_c(CKRX)
3
t_w(CKRX)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
Cycle time, CLKR/X
CLKR/X int
Pulse duration, CLKR/X high or
CLKR/X low
CLKR/X int
4
t_d(CKRH-FRV)
Delay time, CLKR high to internal FSR ^{CLKR int}
valid
CLKR ext
9
t_d(CKXH-FXV)
Delay time, CLKX high to internal FSX ^{CLKX int}
valid
CLKX ext
12
t_dis(CKXH-
DXHZ)
Disable time, DX high impedance
CLKX int
following last data bit from CLKX high _{CLKX ext}
13 t_d(CKXH-DXV) Delay time, CLKX high to DX valid
CLKX int
CLKX ext
14 t_d(FXH-DXV)
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX int
FSX ext
1.3V, 1.2V
MIN
MAX
2
14.5
2P or 20 ^{(3) (4) (5)}
C - 2⁽⁶⁾
C + 2⁽⁶⁾
-4
2
-4
2
-4
-2
-4 + D1⁽⁷⁾
2 + D1⁽⁷⁾
-4 ⁽⁸⁾
5.5
14.5
5.5
14.5
7.5
16
5.5 + D2⁽⁷⁾
14.5 + D2⁽⁷⁾
5 ⁽⁸⁾
-2 ⁽⁸⁾
14.5 ⁽⁸⁾
1.1V
MIN
MAX
2
16
2P or 25^{(3) (4) (5)}
C - 2⁽⁶⁾
C + 2⁽⁶⁾
-4
2
-4
2
-5.5
-22
-4 + D1⁽⁷⁾
2 + D1⁽⁷⁾
-4 ⁽⁸⁾
5.5
16
5.5
16
7.5
16
5.5 + D2⁽⁷⁾
16 + D2⁽⁷⁾
5 ⁽⁸⁾
-2 ⁽⁸⁾
16 ⁽⁸⁾
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
128 Specifications
Submit Documentation Feedback
Product Folder Links: SM320C6748-HIREL
Copyright © 2016, Texas Instruments Incorporated