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TAS3103_12 Datasheet, PDF (122/150 Pages) Texas Instruments – Digital Audio Processor With 3D Effects
4.4.5 I2C Slave Mode Interface Signals Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER
TEST
CONDITIONS
STANDARD MODE
MIN TYP
MAX
FAST MODE
MIN TYP
UNITS
MAX
fSCL Frequency, SCL
tW(H)
Minimum pulse duration,
SCL high
See Note 15
0
100
0.43
0
0.12
400 kHz
µs
tW(L)
Minimum pulse duration,
SCL low
See Note 15
1.3
0.9
µs
tr
Rise time, SDAOutput
CL = 330 pF
48.3
48.3 ns
tf
Fall time, SDAOutput
CL = 330 pF
35.9
35.9 ns
tsu1 Setup time, SDAInput to SCL See Note 15
0
0
ns
Hold SCL to SDAInput
See Note 15
0
th1
time SCL to SDAOutput See Note 16
Toversamp
0
2Toversamp Toversamp
ns
2Toversamp µs
Minimum bus free time
tbuf between STOP and START See Note 15
0.82
condition
0.38
µs
tsu2
Minimum setup time, SCL to
START condition
See Note 15
0.7
0.4
µs
th2
Minimum hold time, START
condition to SCL
See Note 15
1.5
0.05
µs
tsu3
Minimum setup time, SCL to
STOP condition
See Note 15
0.9
0.4
µs
NOTES: 15. The maximum and/or minimum values for the TAS3103 I2C port parameters meets those characteristics of the SDA and SCL bus
lines listed below, as specified in the I2C bus devices bus specification.
16. Toversamp is the period of the oversample clock provided to the I2C master salve controller. This clock is dependent on the
microprocessor clock setting and the value set for the variable N in subaddress 0xFB. See Figure 2−14.
SCL
SDAInput
START/STOP conditions
SPECIFIED I2C BUS CHARACTERISTICS
PARAMETER
Pulse duration high, tw(H)
Pulse duration low, tw(L)
Frequency fSCL
Setup time tsu1, SDAInput to SCL
Hold Time th1, SCL to SDAInput
Bus free time between STOP and START condition tbuf
Setup time tsu2, SCL to START condition
Hold time th2, START condition to SCL
Setup time tsu3, SCL to STOP condition
STANDARD MODE
4 µs MIN
4.7 µs MIN
100 kHz
250 ns MIN
0 ns MIN
4.7 µs MIN
4.7 µs MIN
4 µs MIN
4 µs MIN
FAST MODE
0.6 µs MIN
1.3 µs MIN
400 kHz
100 ns MIN
0 ns MIN
1.3 µs MIN
0.6 µs MIN
0.6 µs MIN
0.6 µs MIN
4−7