UCC28521_16 Datasheet, PDF (12/34 Pages) Texas Instruments – ADVANCED PFC/PWM COMBINATION CONTROLLER

UCC28521, UCC28528
SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION
design procedure
The following discussion steps through the typical design process of a PFC/PWM converter system. The design
process begins with the power stage elements, then the control elements for the PFC stage, then the control
elements for the PWM stage. Keep in mind that a general design process is often iterative. Iteration typically
begins after either simulating and/or testing the completed PFC/PWM system. This design procedure refers to
the typical application in Figure 1.
A design begins with a list of requirements for output voltage, output power and ac line voltage range. Other
details, such as efficiency and permissible current harmonics could be given at the onset, or developed
throughout the product design cycle. The need for power factor correction arises from either an agency
requirement, such as EN−61000, or if the available line power is nearly equal to the output power of the power
system. Hold-up time requirements are also necessary at the early stages of design. Typically, the hold-up time,
t_HU, is at least the period of 1.5 line cycles.
The general structure of the PFC/PWM stage power system is two switched-mode converters connected in
cascade. Each stage has an associated efficiency and each stage has its own set of fault limiting controls that
must be properly set in order to achieve the desired line harmonic and load regulation performance,
simultaneously. The PFC stage must always be designed to supply sufficient average power to the PWM stage.
The cycle-by-cycle current limit of the PFC stage should be programmed to activate at a slightly larger power
level at low ac line voltage than the average power clamp in order to allow for PFC current sense tolerances.
This will allow power factor correction for the full range of maximum rated load. If the instantaneous load nearly
equals the average load, then the fault clamps for the PWM stage can be programmed to limit power at a level
that is slightly less than or equal to the average power clamp of the PFC stage. The margin for the clamping
action should allow for measurement tolerances and efficiency. Conversely, if the instantaneous load has high
peaks that are much shorter than the hold-up time, the current limit and duty ratio limits of the PWM stage can
clamp at a higher level than the average power clamp in the PFC stage. In order to simplify the design procedure,
the average and the peak loads of the PWM stage are assumed to be equal. Thus, all of the current limits and
duty cycle limits are programmed to clamp power at a slightly lower level (10%) than the average power clamp
on the PFC stage.
developing the internal parameters
Select the energy storage voltage V_C1. Since the PFC stage is a boost converter, the voltage across C1 must
be larger than the peak ac line voltage by enough to permit controllability in the event of load transients. Typically,
this will be around 5% which is about 400 V for a universal ac line application of 85 V_AC to 265 V_AC.
Once the energy storage voltage, V_C1, is determined, the range of the PFC stage duty ratio, D₁, is set. For CCM
operation of the PFC stage, the minimum PFC duty ratio is given by:
Ǹ₂
D_1(min) + 1 *
VAC_MIN
V_C1
(1)
12
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