TPS79101-EP_16 Datasheet, PDF (12/23 Pages) Texas Instruments – ULTRALOW NOISE, HIGH PSRR, FAST RF, 100-mA LOW-DROPOUT LINEAR REGULATORS

TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
SGLS161A – APRIL 2003 – REVISED JUNE 2008 ............................................................................................................................................................ www.ti.com
Power Dissipation and Junction Temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P_D(max), and the actual dissipation, P_D, which must be less than or
equal to P_D(max).
The maximum power-dissipation limit is determined using the following equation:
PD(max)
+
TJmax *
R_qJA
TA
(1)
Where:
T_Jmax is the maximum allowable junction temperature.
R_θJA is the junction-to-ambient thermal resistance for the package (see the dissipation rating table).
T_A is the ambient temperature.
The regulator dissipation is calculated using:
ǒ Ǔ PD + VI * VO IO
(2)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
Programming the TPS79101 Adjustable LDO Regulator
The output voltage of the TPS79101 adjustable regulator is programmed using an external resistor divider as
shown in Figure 34. The output voltage is calculated using:
ǒ Ǔ VO + Vref
1
)
R1
R2
(3)
Where:
V_ref = 1.2246 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should be
avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and thus erroneously decreases/increases V_O. The recommended
design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA, C1 = 15 pF for stability, and then
calculate R1 using:
ǒ Ǔ R1 +
VO
Vref
*
1
R2
(4)
In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be
placed between OUT and FB. For voltages <1.8 V, the value of this capacitor should be 100 pF. For
voltages > 1.8 V, the approximate value of this capacitor can be calculated as:
C1 + ⁽³
10^*7)
(R1
(R1 ) R2)
R2)
(5)
The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is
not used (such as in a unity-gain configuration) or if an output voltage < 1.8 V is chosen, then the minimum
recommended output capacitor is 2.2 µF instead of 1 µF.
12
Submit Documentation Feedback
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP