TPS65132_16 Datasheet, PDF (12/64 Pages) Texas Instruments – Single Inductor - Dual Output Power Supply

TPS65132
SLVSBM1G – JUNE 2013 – REVISED AUGUST 2015
8 Detailed Description
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8.1 Overview
The TPS65132, supporting input voltage range from 2.5 V to 5.5 V, operates with a single inductor scheme to
provide a high efficiency with a small solution size. The synchronous boost converter generates a positive
voltage that is regulated down by an integrated LDO, providing the positive supply rail (V_POS). The negative
supply rail (V_NEG) is generated by an integrated negative charge pump (or CPN) driven from the boost converter
output pin REG. The operating mode can be selected between Smartphone and Tablet in order to select the
necessary output current capability and to get the best efficiency possible based on the application. The device
topology allows a 100% asymmetry of the output currents.
8.2 Functional Block Diagram
V_IN
(battery voltage)
SW
VIN SYNC
BOOST
REG
LDO
OUTP
ENP
ENN
SCL
SDA
CPN
OUTN
AGND
V_POS
5.4 V/40 mA
V_NEG
–5.4 V/40 mA
8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
The TPS65132 integrates an undervoltage lockout block (UVLO) that enables the device once the voltage on the
VIN pin exceeds the UVLO threshold (2.5 V maximum). No output voltage will however be generated as long as
the enable signals are not pulled HIGH. The device, as well as all converters (boost converter, LDO, CPN), will
be disabled as soon as the V_IN voltage falls below the UVLO threshold. The UVLO threshold is designed in a
way that the TPS65132 will continue operating as long as V_IN stays above 2.3 V. This guarantees a proper
operation even in the event of extensive line transients when the battery gets suddenly heavily loaded.
For TPS65132Ax, a 40 ms delay is starting as soon as the UVLO threshold is reached. This delay prevents the
device to be disabled and enabled by an unwanted VIN voltage spike. Once this delay has passed, the output
rails can be enabled and disabled as desired with the enable signals without any delay.
8.3.2 Active Discharge
An active discharge of the positive rail and/or the negative rail can be programmed (DISP and DISN bits
respectively - refer to DAC Registers). If programmed to be active, the discharge will occur at power down, when
the enable signals go LOW (Figure 41 and Figure 42 for TPS65132Ax, Bx, Lx, Wx — Figure 42 and Figure 41 for
TPS65132Sx). See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed
description of how each device variant implements the active discharge function.
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