TPS54335 Datasheet, PDF (12/37 Pages) Texas Instruments – 4.5V to 28V Input, 3A Output, Synchronous Step Down SWIFT™ Converter

TPS54335
TPS54336
SLVSC03 – MAY 2013
1000
RT SET RESISTOR
vs
OSCILLATOR FREQUENCY
800
600
400
200
0
0
250
500
750
1000
1250
1500
Fsw - Oscillator Frequency - kHz
Figure 16. RT Set Resistor vs Switching Frequency
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SLOW START (TPS54336 ONLY)
The device uses the lower voltage of the internal voltage reference or the SS pin voltage as the reference
voltage and regulates the output accordingly. A capacitor on the SS pin to ground implements a slow start time.
The device has an internal pull-up current source of 2.3 μA that charges the external slow start capacitor. The
calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in Equation 5.
The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3μA.
Tss(ms) = ^{Css(nF) ´ Vref(V)}
Iss(m A)
(5)
When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the
device stops switching and enters low current operation. At the subsequent power up, when the shutdown
condition is removed, the device does not start switching until it has discharged its SS pin to ground ensuring
proper soft start behavior.
OUTPUT OVERVOLTAGE PROTECTION (OVP)
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier demands maximum output current. Once the condition is
removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some
applications with small output capacitance, the power supply output voltage can respond faster than the error
amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by
comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP
threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to
turn on at the next clock cycle.
OVERCURRENT PROTECTION
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
High-side MOSFET overcurrent protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-
side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared, when the peak switch current
intersects the current reference the high-side switch is turned off.
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