TPS40210-EP_16 Datasheet, PDF (12/41 Pages) Texas Instruments – 4.5-V to 52-V Input Current Mode Boost Controller

TPS40210-EP
SLUSC89 – NOVEMBER 2015
www.ti.com
7.3 Feature Description
7.3.1 Soft-Start
The soft-start feature of the TPS40210-EP is a closed-loop soft-start, meaning that the output voltage follows a
linear ramp that is proportional to the ramp generated at the SS pin. This ramp is generated by an internal
resistor connected from the BP pin to the SS pin and an external capacitor connected from the SS pin to GND.
The SS pin voltage (V_SS) is level shifted down by approximately V_SS(ofst) (approximately 700 mV) and sent to one
of the “+” (the “+” input with the lowest voltage dominates) inputs of the error amplifier. When this level shifted
voltage (V_SSE) starts to rise at time t₁ (see Figure 20), the output voltage the controller expects, rises as well.
Since V_SSE starts at near 0 V, the controller attempts to regulate the output voltage from a starting point of zero
volts. It cannot do this due to the converter architecture. The output voltage starts from the input voltage less the
drop across the diode (V_IN – V_D) and rises from there. The point at which the output voltage starts to rise (t₂) is
the point where the V_SSE ramp passes the point where it is commanding more output voltage than (V_IN – V_D).
This voltage level is labeled V_SSE(1). The time required for the output voltage to ramp from a theoretical zero to
the final regulated value (from t₁ to t₃) is determined by the time it takes for the capacitor connected to the SS pin
(C_SS) to rise through a 700-mV range, beginning at V_SS(ofst) above GND.
V_SS
V_SS(ofst)+700 mV
V_SS(ofst)
t₀
t₁
V_IN - V_D
t₂ t₃
V_SSE
V_SSE(1)
V_OUT
SS
2
R_SS(chg)
R_SS(dchg)
TPS40210-EP
700 mV REF
Error Amplifier
+
+
FB
5
COMP
4
DIS
UVLO
OC Fault
Figure 20. SS Pin Voltage and Output Voltage
UDG-07121
Figure 21. SS Pin Functional Circuit
12
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