TP11368_11 Datasheet, PDF (12/20 Pages) Texas Instruments – Octal Adaptive Differential PCM Processor

Timing Specifications (Continued)
Unless otherwise noted, limits
−40˚C to +85˚C by correlation
printed in bold characters are
with 100% electrical testing at
guaranteed
T_A = 25˚C.
for V_CC = 5.0V ± 5%, GND1 = GND2 =
All other limits are assured by correlation
0V, T_A =
with other
production tests and/or product design and characterization. Typical values are specified at V_CC = +5V, T_A = 25˚C.
Symbol
Parameter
Conditions
Min
Typ Max
Units
t_HDCEL
Hold Time, CE low after
PSCK/ASCK High
15
ns
t_SUCEH
Setup Time, CE High Before
PSCK/ASCK Low
15
ns
t_TRBH
TRB Hold Time
From CE Low
20
ns
t_TRBS
TRB Setup Time
From ASCK Low and PSCK Low
20
ns
t_IS
TSI, RSI Setup Time
From ASCK Low and PSCK Low
20
ns
t_IH
TSI, RSI Hold Time
From ASCK Low and PSCK Low
20
ns
t_PSCK/ASCK
PSCK/ASCK High and
55
ns
Low Times
t_ON
TSO, RSO Turn On Time
From CE High
t_OD
TSO, RSO Propagation
From ASCK High or PSCK High
Delay Time
40
ns
40
ns
t_OFF
TSO, RSO Turn Off Time
From CE Low
(Valid Data to TRI-STATE)
20
ns
t_CS
Setup Time for Control
From CE Low
Signals (INIT, EN,
20
ns
PCM1, QSEL1, QSEL0)
t_CH
Hold Time for Control
From CE Low
Signals (INIT, EN,
20
ns
PCM1, QSEL1, QSEL0)
t_RSTL
RSTB Pulse Width Low
2
CLK
Cycles
t_RSTH
RSTB High to the First
CE High-Low Transition
6
CLK
Cycles
Note 5: Values for 8 full-duplex (decoding and encoding) or 16 half-duplex (decoding or encoding) channels operation in a 125 µs period.
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