TNETE100PM Datasheet, PDF (12/27 Pages) Texas Instruments – PCI ETHERNETE CONTROLLER WITH POWER MANAGEMENT SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

ThunderLAN™ TNETE100PM
PCI ETHERNET™ CONTROLLER WITH POWER MANAGEMENT
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS026 – OCTOBER 1996
absolute maximum ratings over operating case temperature range (unless otherwise noted)^†
Supply voltage range, V_DD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Operating case temperature range, T_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 95°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: Voltage values are with respect to VSS, and all VSS pins should be routed so as to minimize inductance to system ground.
The recommended operating conditions and the electrical characteristics tables are divided into groups,
depending on pin function:
D PCI-interface pins
D Logic pins
D Physical-layer pins
The PCI signal pins are operated in one of two modes shown in the PCI tables.
D 5-V signal mode
D 3-V signal mode
recommended operating conditions (PCI-interface pins only) (see Note 3)
3-V SIGNALING
OPERATION
MIN
NOM
MAX
5-V SIGNALING
OPERATION
MIN NOM MAX
UNIT
VDD
VIH
VIL
IOH
IOL
Supply voltage (PCI)
High-level input voltage
Low-level input voltage, TTL-level signal (see Note 4)
High-level output current
TTL outputs
Low-level output current (see Note 5) TTL outputs
3
 0.5 VDD
– 0.5
3.3
3.6
VDD + 0.5
 0.3 VDD
– 0.5
1.5
4.75
2.0
– 0.5
5 5.25
V
VDD + 0.5
V
0.8
V
–2
mA
6
mA
TC Operating case temperature
0
95
0
95
°C
Tstg Storage temperature
– 65
150
– 65
150
°C
NOTES: 3. PCI interface pins include PCLKRUN, PFRAME, PTRDY, PIRDY, PSTOP, PDEVSEL, PIDSEL, PPERR, PSERR, PREQ, PGNT,
PCLK, PPAR, PRST, PINTA, PAD[31 : 0], and PC/BE[3 : 0].
4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
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