TLC4541_14 Datasheet, PDF (12/28 Pages) Texas Instruments – 5-V LOW POWER, 16-BIT, 200-KSPS SEREAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

TLC4541, TLC4545
SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
control and timing
device initialization/RESET cycle
The TLC4541/45 each require one RESET cycle after power-on for initialization in order to operate properly.
This RESET cycle is initiated by asserting the CS pin (pin 1) low for a minimum duration of at least one SCLK
falling edge but no more than 8 SCLK falling edges in length. The RESET cycle is terminated by asserting CS
high. If a valid RESET cycle is issued, the data presented on the SDO output during the following cycle is FF00h.
This output code is useful in determining when a valid reset/initialization has occurred.
The TLC4541 has separate CS and FS pins. In this case, it is also possible to initiate the RESET cycle by
asserting FS low if CS is already low. The RESET cycle can be terminated by either asserting CS high (as shown
in the first RESET cycle in Figure 14), or by asserting FS high ( as shown in the second RESET cycle in Figure
14), whichever happens first.
SCLK
12 8
12 8
1
4
16
1
4
tcyc(reset)
CS
OR
tcyc(reset)
FS
FS High for Valid Initialization
1−8 Falling SCLK Edges−
ÎÎÎÎÎÎÎÎÎÎÎ ^SDO
ADC is Initialized
Normal Cycle−Sample
and Convert
1111−1111−0000−0000
t(PWRDWN)
Normal Cycle−Sample
and Convert
MSB
LSB−3 LSB
SDO Data−Reset of Previous cycle’s Sample
For TLC45xx−LSB Presented on 16th Rising SCLK Edge
Figure 14. TLC4541/45 Initialization Timing
sampling
The converter sample time is 20 SCLKs in duration, beginning on the 5th SCLK received during an active signal
on the CS input (or FS input for the TLC4541.)
conversion
Each device completes a conversion in the following manner. The conversion is started after the 24th falling
SCLK edge. The CS input can be released at this point or at any time during the remainder of the conversion
cycle. The conversion takes a maximum of 2.94 µs to complete. Enough time (for conversion) should be allowed
before the next falling edge on the CS input (or rising edge on the FS input for the TLC4541) so that no
conversion is terminated prematurely. If the conversion cycle is terminated early, the data presented on SDO
during the following cycle is FF00h. This predefined output code is helpful in determining if the cycle time is not
long enough to complete the conversion. The same code is also used to determine if a reset cycle is valid.
For all devices, the SDO data presented during a cycle is the result of the conversion of the sample taken during
the previous cycle. The output data format is shown in the following table.
TLC4541/45
SERIAL OUTPUT DATA FORMAT
MSB [D15:D2]
LSB [D1:D0]
Conversion Result (OD15−OD2)
Conversion Result (OD1 − OD0)
12
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