SN74LVC1G17_16 Datasheet, PDF (12/39 Pages) Texas Instruments – SN74LVC1G17 Single Schmitt-Trigger Buffer

SN74LVC1G17
SCES351V – JULY 2001 – REVISED APRIL 2014
Typical Application (continued)
10.2.3 Application Curves
10
Icc 1.8V
9
Icc 2.5V
8
Icc 3.3V
Icc 5V
7
6
5
4
3
2
1
0
0
20
40
60
Frequency - MHz
Figure 5. ICC vs Frequency
80
D003
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11 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Specified below are the rules that must
be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or
low bias to prevent them from floating. The logic level that should be applied to any particular unused input
depends on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or
is more convenient.
12.2 Layout Example
V_CC
Unused Input
Input
Output
Input
Unused Input
Output
12
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