SE555-SP Datasheet, PDF (12/18 Pages) Texas Instruments – QML CLASS V PRECISION TIMER

SE555-SP
SGLS401 – FEBRUARY 2010
www.ti.com
Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 10 can be made to operate as a frequency
divider. Figure 18 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during
ÏÏÏÏÏ ^{the timing cycle.}
ÏÏÏÏÏ _{VCC = 5 V}
ÏÏÏÏÏ _{RA = 1250 Ω}
ÏÏÏÏÏ ^{C = 0.02 µF}
ÏÏÏÏÏ ^{See Figure 9}
Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.1 ms/div
Figure 18. Divide-by-Three Circuit Waveforms
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