LP8728-Q1_14 Datasheet, PDF (12/25 Pages) Texas Instruments – LP8728-Q1 Quad-Output Step-Down DC/DC Converter

LP8728-Q1
SNVS972B – AUGUST 2013 – REVISED DECEMBER 2014
Feature Description (continued)
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VIN ^5.7V
OVP
PG_B1
PG_B2
PG_B3
PG_B4
V_OUT1
V_OUT3
V_OUT4
V_OUT2
5 ms
500μs 500μs 500μs
50 ms
Figure 12. OVP Duration Less Than 50 ms
If an overvoltage condition has lasted more than 50 ms, power-good signals are released high once
corresponding output voltage has settled. Regulators are started in a buck1 → buck2 → buck3 → buck4
sequence. A 500-µs delay is included between each buck start-up (Figure 13). If an overvoltage condition has
lasted less than 5 ms, buck converters are not shut down. Even in this case the PG_Bx pins are held low for 50
ms.
NOTE
Since regulators are allowed to operate for 5 ms during overvoltage condition it is the
system designer’s responsibility to verify that input voltage doesn’t exceed limits stated in
Absolute Maximum Ratings. Exceeding these limits may cause permanent damage to the
device.
VIN 5.7V
OVP
PG_B1
PG_B2
PG_B3
PG_B4
V_OUT1
V_OUT3
V_OUT4
V_OUT2
5 ms
50 ms
500μs 500μs 500μs
Figure 13. OVP Duration More Than 50 ms
12
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