LM4937 Datasheet, PDF (12/41 Pages) Texas Instruments – Audio Sub-System with OCL Stereo Headphone Output and RF Suppression

LM4937
SNAS369J – OCTOBER 2006 – REVISED MAY 2013
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
Register
D7
Mode Control
0
Output Control
0
Mono Volume Control
Loud Speaker Volume
Control
RESERVED
Headphone Left
Volume Control
Headphone Right Volume
Control
Analog R & L Input Gain
Control
Analog Mono & DAC Input
Gain Control
Clock Configu
ration
PLL M Divider
PLL N Divider
PLL N_MOD Divider
and Dither Level
PLL_P Divider
DAC Setup
Interface
COMPENSATION _C
OEFF0_LSB
COMPENSATION _C
OEFF0_MSB
COMPENSATION _C
OEFF1_LSB
COMPENSATION _C
OEFF1_MSB
COMPENSATION _C
OEFF2_LSB
COMPENSATION _C
OEFF2_MSB
TEST_
REGISTER
0
0
0
0
0
0
0
R_DIV_3
0
PLL_N_7
VCO_FAST
0
0
0
COMP0_7
COMP0_15
COMP1_7
COMP1_15
COMP2_7
COMP2_15
RESERVED
D6
CD_6
D_6
0
0
0
0
0
0
DIG_R_
GAIN_1
R_DIV_2
PLL_M_6
PLL_N_6
PLL_DITH_LEV_1
0
CUST_COMP
0
COMP0_6
COMP0_14
COMP1_6
COMP1_14
COMP2_6
COMP2_14
RESERVED
(1) Note: All registers default to 0 on initial power-up.
Table 6. Control Registers⁽¹⁾
D5
D4
D3
0
OCL
CD_3
0
0
HP_R_
OUTPUT
0
EP_VOL_4
EP_VOL_3
0
LS_VOL_4
LS_VOL_3
0
0
0
0
HP_L_VOL_4
HP_L_VOL_3
0
HP_R_VOL_4
HP_R_VOL_3
ANA_R_
GAIN_2
DIG_R_
GAIN_0
R_DIV_1
PLL_M_5
PLL_N_5
PLL_DITH_LEV_0
ANA_R_
GAIN_1
DIG_L_
GAIN_1
R_DIV_0
PLL_M_4
PLL_N_4
PLL_N_MOD_4
ANA_R_
GAIN_0
DIG_L_
GAIN_0
PLL_
ENABLE
PLL_M_3
PLL_N_3
PLL_N_MOD_3
0
DITHER_ALW_ON
0
COMP0_5
0
DITHER_OFF
0
COMP0_4
PLL_P_3
MUTE_R
I2C_FAST
COMP0_3
COMP0_13
COMP0_12
COMP0_11
COMP1_5
COMP1_4
COMP1_3
COMP1_13
COMP1_12
COMP1_11
COMP2_5
COMP2_4
COMP2_3
COMP2_13
COMP2_12
COMP2_11
RESERVED
RESERVED
RESERVED
D2
CD_2
HP_L_
OUTPUT
EP_VOL_2
LS_VOL_2
0
HP_L_VOL_2
HP_R_VOL_2
ANA_L_
GAIN_2
MONO_IN_
GAIN_2
AUDIO
_CLK_SEL
PLL_M_2
PLL_N_2
PLL_N_MOD_2
PLL_P_2
MUTE_L
I2S_MODE
COMP0_2
COMP0_10
COMP1_2
COMP1_10
COMP2_2
COMP2_10
RESERVED
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D1
CD_1
LS_
OUTPUT
EP_VOL_1
LS_VOL_1
0
HP_L_VOL_1
HP_R_VOL_1
ANA_L
_GAIN_1
MONO_IN_
GAIN_1
PLL_INPUT
PLL_M_1
PLL_N_1
PLL_N_MOD_1
PLL_P_1
DAC_MODE_1
I2S_RESOL
COMP0_1
COMP0_9
COMP1_1
COMP1_9
COMP2_1
COMP2_9
RESERVED
D0
CD_0
MONO_
OUTPUT
EP_VOL_0
LS_VOL_0
0
HP_L_VOL_0
HP_R_VOL_0
ANA_L
_GAIN_0
MONO_IN_
GAIN_0
FAST_
CLOCK
PLL_M_0
PLL_N_0
PLL_N_MOD_0
PLL_P_0
DAC_MODE_0
I2S_M/S
COMP0_0
COMP0_8
COMP1_0
COMP1_8
COMP2_0
COMP2_8
RESERVED
12
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