DS8921_15 Datasheet, PDF (12/20 Pages) Texas Instruments – Differential Line Driver and Receiver Pair

DS8921, DS8921A, DS8921AT
SNLS374D – MAY 1998 – REVISED JANUARY 2015
www.ti.com
10 Power Supply Recommendations
TI recommends connecting the supply (VCC) and ground (GND) pins to power planes that are routed on
adjacent layers of the PCB. Additionally, careful attention should be paid to bypassing the supply using a
capacitor. A 0.1-µF bypass capacitor should be connected to the VCC pin such that the capacitor is as close as
possible to the device.
11 Layout
11.1 Layout Guidelines
High-speed interconnects should be treated as transmission lines with a controlled impedance. The differential
interconnect can be a pair of printed-circuit board (PCB) traces, twisted-pair wires, or a parallel wire cable. A
termination resistor should be placed at the differential input, and the resistor value should be approximately the
same as the differential impedance of the transmission line to minimize reflections.
It is preferable to connect the VCC and GND pins to the power and ground planes using plated-through-holes.
Additionally, a 0.1-µF bypass capacitor should be placed close to the VCC pin across VCC and GND.
Place a terminating resistor at the receiving end of the interconnect transmission line, as close as possible to the
input pins of the receiver. The terminating resistor value should be approximately the same as the differential pair
impedance to minimize reflection, and the transmission line should have a controlled impedance with minimum
impedance discontinuities.
The input and output differential signals of the device should have traces that are routed exclusively on one layer
of the board, and the differential pairs should also be routed away from other differential pairs in order to
minimize crosstalk between transmission lines. Additionally, the differential pairs should have a controlled
impedance with minimum impedance discontinuities and be terminated with a resistor that is closely matched to
the differential pair impedance in order to minimize transmission line reflections. The differential pairs should be
routed with uniform trace width and spacing to minimize impedance mismatch.
11.2 Layout Example
Via to GND
Plane
Via to VCC
Plane
1
Bypass Capacitor
5
Termination
Resistor
RX Differential Pair
2
6
DS8921/DS8921A/DS8921AT
3
Via to GND
Plane
4
7
TX Differential Pair
8
Figure 16. DS8921 Example Layout
12
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