DLP2000 Datasheet, PDF (12/40 Pages) Texas Instruments – DLP2000 (.2nHD) DMD

DLP2000
DLPS078 – JULY 2017
DCLK, SCTRL, LOADB, DATA(11:0)
80%
20%
t_R
t_F
Figure 4. Rise and Fall Timing Parameters 1
SAC_CLK, SAC_BUS, DRC_BUS
t_R
80%
20%
t_F
VCC
VSS
Figure 5. Rise and Fall Timing Parameters 2
Device Pin
Output Under Test
Tester Channel
C_LOAD
VCC
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VSS
Not To Scale
Figure 6. Test Load Circuit
See Timing for more information.
6.8 System Mounting Interface Loads
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Maximum system mounting
Connector area (see Figure 7)
interface load to be applied to the: _{DMD mounting area uniformly distributed over 4 areas (see Figure 7)}
MIN NOM MAX UNIT
45
N
100 N
12
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