DAC7617_14 Datasheet, PDF (12/18 Pages) Texas Instruments – Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER

STATE OF
SELECTED
SELECTED
STATE OF
INPUT
INPUT
ALL DAC
A1
A0
LOADREG
LDAC
RESET
REGISTER
REGISTER
REGISTERS
L⁽¹⁾
L
L
H⁽²⁾
H
L
H
L
H
H
H
L
L
H
H
H
H
L
H
H
X⁽³⁾
X
H
L
H
X
X
H
H
H
X
X
X
X
L
A
B
C
D
NONE
NONE
ALL
Transparent
Transparent
Transparent
Transparent
(All Latched)
(All Latched)
Reset⁽⁴⁾
Latched
Latched
Latched
Latched
Transparent
Latched
Reset⁽⁴⁾
NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care. (4) Resets to either 000H or 800_H, per the RESETSEL state (LOW = 000_H, HIGH = 800_H).
When RESET rises, all registers that are in their latched state retain the reset value.
TABLE II. Control Logic Truth Table.
CS⁽¹⁾ CLK⁽¹⁾ LOADREG RESET SERIAL SHIFT REGISTER
H⁽²⁾
X⁽³⁾
H
H
L⁽⁴⁾
L
H
H
L
↑⁽⁵⁾
H
H
↑
L
H
H
H⁽⁶⁾
X
L⁽⁷⁾
H
H⁽⁶⁾
X
H
L⁽⁸⁾
No Change
No Change
Advanced One Bit
Advanced One Bit
No Change
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X
= Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH
value is suggested in order to avoid a “false clock” from advancing the shift
register and changing the shift register. (7) If data is clocked into the serial
register while LOADREG is LOW, the selected input register will change
as the shift register bits “flow” through A1 and A0. This will corrupt the data
in each input register that has been erroneously selected. (8) RESET LOW
causes no change in the contents of the serial shift register.
TABLE III. Serial Shift Register Truth Table.
Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register inter-
nal to the DAC7617 (see the block diagram on the front of
this data sheet). These two inputs are completely inter-
changeable. In addition, care must be taken with the state of
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong input register.
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
The digital data into the DAC7617 is double-buffered. This
allows new data to be entered for each DAC without disturb-
ing the analog outputs. When the new settings have been
entered into the device, all of the DAC outputs can be
updated simultaneously. The transfer from the input regis-
ters to the DAC registers is accomplished with a HIGH to
LOW transition on the LDAC input. It is possible to keep
this pin LOW and update each DAC via LOADREG be-
cause the DAC registers become transparent when LDAC is
LOW. However, as each new data word is entered into the
device, the corresponding output will update immediately
when LOADREG is taken LOW.
Digital Input Coding
The DAC7617 input data is in Straight Binary format. The
output voltage is given by the following equation:
V_OUT
=
V_REFL
+
(V_REFH
– V_REFL)
4096
•
N
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
DAC7617
12
SBAS185