DAC5675A Datasheet, PDF (12/26 Pages) Texas Instruments – 14-Bit, 400MSPS Digital-to-Analog Converter

DAC5675A
SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005
www.ti.com
Digital Inputs
APPLICATION INFORMATION (continued)
The DAC5675A uses a low voltage differential signaling (LVDS) bus input interface. The LVDS features a low
differential voltage swing with low constant power consumption (≈4mA per complementary data input) across
frequency. The differential characteristic of LVDS allows for high-speed data transmission with low
electromagnetic interference (EMI) levels. The LVDS input minimum and maximum input threshold table lists the
LVDS input levels. Figure 14 shows the equivalent complementary digital input interface for the DAC5675A, valid
for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110Ω resistors for proper
termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A common-mode level
of 1.2V and a differential input swing of 0.8V_PP is applied to the inputs.
Figure 15 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675A, valid for
the SLEEP pin.
DV_DD
DAC5675A
DAC5675A
D[13..0]A
D[13..0]B
Internal
Digital IN
110Ω
Termination
Resistor
D[13..0]A
Internal
Digital In
D[13..0]B
DGND
Figure 14. LVDS Digital Equivalent Input
DV_DD
DAC5675A
Digital Input
Internal
Digital In
DGND
Figure 15. CMOS/TTL Digital Equivalent Input
Clock Input
The DAC5675A features differential, LVPECL compatible clock inputs (CLK, CLKC). Figure 16 shows the
equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage
to approximately 2V, while the input resistance is typically 670Ω. A variety of clock sources can be ac-coupled to
the device, including a sine wave source (see Figure 17).
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