ADC121S021_14 Datasheet, PDF (12/24 Pages) Texas Instruments – ADC121S021 Single Channel, 50 to 200 ksps, 12-Bit A/D Converter

ADC121S021
SNAS305I – JULY 2005 – REVISED JANUARY 2014
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Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading
zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent
rising edges of SCLK. The ADC will produce three leading zero bits on SDATA, followed by twelve data bits,
most significant first.
If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling
edge of SCLK.
Determining Throughput
Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one
conversion and the start of another. At the maximum specified SCLK frequency, the maximum ensured
throughput is obtained by using a 20 SCLK frame. As shown in Figure 3, the minimum allowed time between CS
falling edges is determined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two quantities: either the minimum
required time for Track mode (t_ACQ) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2 or 1 SCLK padding to
ensure an even number of SCLK cycles so there is a falling SCLK edge when CS next falls. For example, at the
fastest rate for this family of parts, SCLK is 20MHz and 2.5 SCLKs are 125ns, so the minimum time between CS
falling edges is calculated by:
12.5*50ns + 350ns + 0.5*50ns = 1000ns
(2)
(12.5 SCLKs + t_ACQ + 1/2 SCLK) which corresponds to a maximum throughput of 1MSPS. At the slowest rate for
this family, SCLK is 1MHz. Using a 20 cycle conversion frame as shown in Figure 3 yields a 20μs time between
CS falling edges for a throughput of 50KSPS.
It is possible, however, to use fewer than 20 clock cycles provided the timing parameters are met. With a 1MHz
SCLK, there are 2500ns in 2.5 SCLK cycles, which is greater than t_ACQ. After the last data bit has come out, the
clock will need one full cycle to return to a falling edge. Thus the total time between falling edges of CS is
12.5*1μs +2.5*1μs +1*1μs=16μs which is a throughput of 62.5KSPS.
ADC121S021 TRANSFER FUNCTION
The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB
values. The LSB width for the ADC is V_A/4096. The ideal transfer characteristic is shown in Figure 18. The
transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of
V_A/8192. Other code transitions occur at steps of one LSB.
111...111
111...110
111...000
|
011...111
1 LSB = V_A/4096
000...010
000...001
000...000
0V ^{0.5 LSB}
ANALOG INPUT
+V_A-1.5 LSB
Figure 18. Ideal Transfer Characteristic
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