LM3S9B96-IQC80-C5T Datasheet, PDF (1175/1400 Pages) Texas Instruments – Stellaris® LM3S9B96 Microcontroller

Stellaris^® LM3S9B96 Microcontroller
Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 17: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
Register 18: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
Register 19: PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt,or an ADC trigger are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the PWMnCMPA register while counting up
■ The counter being equal to the PWMnCMPA register while counting down
■ The counter being equal to the PWMnCMPB register while counting up
■ The counter being equal to the PWMnCMPB register while counting down
Any combination of these events can generate either an interrupt or an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified. The PWMnRIS register provides information about which events have caused raw
interrupts.
PWM0 Interrupt and Trigger Enable (PWM0INTEN)
PWM0 base: 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Type
Reset
15
14
reserved
RO
RO
0
0
13
12
11
10
9
8
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
7
6
reserved
RO
RO
0
0
5
4
3
2
1
0
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit/Field
31:14
13
Name
reserved
TRCMPBD
Type
RO
R/W
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Trigger for Counter=PWMnCMPB Down
Value Description
1 An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting down.
0 No ADC trigger is output.
January 20, 2012
Texas Instruments-Production Data
1175