TMS320C6414EGLZA6E3 Datasheet, PDF (116/145 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146L − FEBRUARY 2001 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
timing requirements for McBSP^† (see Figure 51)
−5E0, A−5E0,
−6E3, A−6E3,
NO.
−7E3
UNIT
MIN
MAX
2
t_c(CKRX)
Cycle time, CLKR/X
CLKR/X ext
4P or 6.67^{द}
ns
3
t_w(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
0.5t_c(CKRX) − 1^#
ns
CLKR int
9
5
t_su(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR ext
1.3
ns
CLKR int
6
6
t_h(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR ext
3
ns
CLKR int
8
7
t_su(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext
0.9
ns
CLKR int
3
8
t_h(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext
3.1
ns
CLKX int
9
10 t_su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
1.3
ns
CLKX int
6
11 t_h(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based}
on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
¶ _{Use whichever value is greater.}
# _{This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.}
116
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443