English
Language : 

TMS320F28027_12 Datasheet, PDF (111/129 Pages) Texas Instruments – Piccolo Microcontrollers
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com
SPRS523I – NOVEMBER 2008 – REVISED JULY 2012
6.11.11 On-Chip Analog-to-Digital Converter
Table 6-38. ADC Electrical Characteristics
PARAMETER
MIN
TYP
MAX UNIT
DC SPECIFICATIONS
Resolution
12
Bits
ADC clock
60-MHz device
0.001
60 MHz
Sample Window
28027/26/23/22
7
28021/20/200
14
64 ADC
64 Clocks
ACCURACY
INL (Integral nonlinearity) at ADC Clock ≤ 30 MHz(1)
–4
4 LSB
DNL (Differential nonlinearity) at ADC Clock ≤ 30 MHz,
no missing codes
Offset error (2)
Executing Device_Cal
function
–1
1 LSB
–20
0
20 LSB
Executing periodic self-
recalibration (3)
–4
0
4
Overall gain error with internal reference
–60
60 LSB
Overall gain error with external reference
–40
40 LSB
Channel-to-channel offset variation
–4
4 LSB
Channel-to-channel gain variation
–4
4 LSB
ADC temperature coefficient with internal reference
–50
ppm/°C
ADC temperature coefficient with external reference
–20
ppm/°C
VREFLO
VREFHI
ANALOG INPUT
–100
µA
100
µA
Analog input voltage with internal reference
0
3.3
V
Analog input voltage with external reference
VREFLO input voltage(4)
VREFHI input voltage(5)
Input capacitance
with VREFLO = VSSA
VREFLO
VSSA
1.98
VREFHI
V
VSSA
V
VDDA
V
5
pF
Input leakage current
±5
μA
(1) INL will degrade when the ADC input voltage goes above VDDA.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed
as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration"
section of the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide (literature number
SPRUGE5).
(4) VREFLO is always connected to VSSA.
(5) VREFHI must not exceed VDDA when using either internal or external reference modes. Since VREFHI is tied to ADCINA0, the input signal
on ADCINA0 must not exceed VDDA.
Copyright © 2008–2012, Texas Instruments Incorporated
Electrical Specifications 111
Submit Documentation Feedback
Product Folder Link(s): TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200