TPS40052_16 Datasheet, PDF (11/30 Pages) Texas Instruments – WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER

TPS40052
SLUS563C − AUGUST 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
PROGRAMMING SOFT START
TPS40052 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start
is programmed by charging an external capacitor (C_SS) via an internally generated current source. The voltage
on C_SS is fed into a separate non-inverting input to the error amplifier (in addition to FB and EA_REF). The loop
is closed on the lower of the C_SS voltage or the the external reference voltage EA_REF. Once the C_SS voltage
rises above the external reference voltage, regulation is based on the external reference. To ensure a controlled
ramp-up of the output voltage the soft-start time should be greater than the L-C_O time constant as described
in equation (9).
t_START w 2p ^ǸL C_O (seconds)
(9)
There is a direct correlation between t_START and the input current required during start-up. The faster t_START,
the higher the input current required during start-up. This relationship is describe in more detail in the section
titled, Programming the Current Limit which follows. The soft-start capacitance, C_SS, is described in
equation (10).
For applications in which the V_IN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be
necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO
tripping. The soft-start time should be longer than the time that the V_IN supply transitions between 8 V and 9 V.
C_SS
+
2.3 mA
0.7 V
t_START (Farads)
(10)
PROGRAMMING CURRENT LIMIT
The TPS40052 uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.
The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is
issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this
period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the
PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the
counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 3 for typical
overcurrent protection waveforms.
The minimum current limit setpoint (I_LIM) depends on t_START, C_O, V_O, and the load current at turn-on (I_L).
ƪ ƫ I_LIM +
ǒ_{CO VO}Ǔ
t_START
) I_L (Amperes)
(11)
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