TMP112-Q1 Datasheet, PDF (11/33 Pages) Texas Instruments – TMP112-Q1 Automotive Grade High-Accuracy, Low-Power, Digital Temperature Sensor in SOT563

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TMP112-Q1
SLOS887D – SEPTEMBER 2014 – REVISED DECEMBER 2015
7.3.2 Serial Interface
The TMP112-Q1 device operates as a slave device only on the I²C, SMBus and two-wire interface-compatible
bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The SDA and SCL pins
feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus
noise. The TMP112-Q1 device supports the transmission protocol for both fast (1 kHz to 400 kHz) and high-
speed (1 kHz to 2.85 MHz) modes. All data bytes are transmitted MSB first.
7.3.2.1 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a high-
to low-logic level when the SCL pin is high. All slaves on the bus shift in the slave address byte on the rising
edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock
pulse, the slave being addressed responds to the master by generating an acknowledge and pulling the SDA pin
low.
A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the data
transfer the SDA pin must remain stable when the SCL pin is high, because any change in the SDA pin when the
SCL pin is high is interpreted as a START or STOP signal.
When all data have been transferred, the master generates a STOP condition indicated by pulling the SDA pin
from low to high when the SCL pin is high.
7.3.2.2 Serial Bus Address
To communicate with the TMP112-Q1 device, the master must first address slave devices through a slave-
address byte. The slave-address byte consists of seven address bits and a direction bit indicating the intent of
executing a read or write operation.
The TMP112-Q1 device features an address pin to allow up to four devices to be addressed on a single bus.
Table 4 lists the pin logic levels used to properly connect up to four devices.
Table 4. Address Pin and Slave Addresses
DEVICE TWO-WIRE ADDRESS
1001 000
1001 001
1001 010
1001 011
A0 PIN CONNECTION
Ground
V+
SDA
SCL
7.3.2.3 Writing and Reading Operation
Accessing a particular register on the TMP112-Q1 device is accomplished by writing the appropriate value to the
pointer register. The value for the pointer register is the first byte transferred after the slave address byte with the
R/W bit low. Every write operation to the TMP112-Q1 device requires a value for the pointer register (see
Figure 11).
When reading from the TMP112-Q1 device, the last value stored in the pointer register by a write operation is
used to determine which register is read by a read operation. To change the register pointer for a read operation,
a new value must be written to the pointer register. This action is accomplished by issuing a slave-address byte
with the R/W bit low, followed by the pointer register byte. No additional data are required. The master can then
generate a START condition and send the slave address byte with the R/W bit high to initiate the read command.
See Figure 12 for details of this sequence. If repeated reads from the same register are desired, continuously
sending the pointer register bytes is not necessary because the TMP112-Q1 device retains the pointer register
value until the value is changed by the next write operation.
Register bytes are sent with the most significant byte first, followed by the least significant byte.
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