THS6226 Datasheet, PDF (11/20 Pages) Texas Instruments – Gated-Class H, Dual-Port VDSL2 Line Driver

THS6226
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SBOS499B – JANUARY 2011 – REVISED FEBRUARY 2011
PROGRAMMING THE THS6226
Programming of the THS6226 is realized through a serial interface (pins 4 and 5) and proceeds in the following
sequence.
Two start bits are required B0 = 0 followed by B1 = 1.
B2 through B9 are used to program the THS6226.
Refer to Table 1 for the bit descriptions.
B10 (refer to Table 2) is the parity bit that controls if the word is or is not loaded.
B11 is the stop bit and should be set to B11 = 1. Figure 21 shows the sequence to be adopted.
PARAMETER
B0, B1
B2, B3
B4, B5
B6-B9
B10
B11
Table 1. SDATA
DESCRIPTION
Start bit
Channel select
Power-down features
Quiescent current setting
Parity bit
Stop bit
B10
0
1
DATA
Table 2. Parity Bit
ODD PARITY BIT
If odd, number of high bits in B2 to B9
If even, number of high bits in B2 to B9
MSB
B0
B1 B2
B3
B4
B5
B6
B7 B8
Start Start Ch AB Ch CD PD1 PD0 D3 D2 D1
Bit
Bit Select Select
Figure 21. DATA Description
LSB
B9 B10 B11
D0 Parity Stop
Bit
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