SN75DP130 Datasheet, PDF (11/31 Pages) Texas Instruments – DisplayPort1:1 Re-Driver with Link Training

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SN75DP130
SLLSE57 – APRIL 2011
TP
HPD_SNK
HPD_SRC
TP
130 KW
100 KW
SN75DP130
HPD_SNK
VCC
50%
0V
tPD(HPD)
VCC ^HPD_SRC
50%
Figure 7. HPD Test Circuit
HPD_SNK
V_CC
50%
0V
HPD_SRC
V_OH
VOL
Sink Hot Plug
Detect Timeout
tT(HPD)
50%
Device active
Low power
0V
Figure 8. HPD Timing Diagram 1
Figure 9. HPD Timing Diagram 2
AUX/DDC/I²C ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
V_PASS
C_IO
r_ON
Δr_ON
V_ID(HYS)
I_H
I_L
V_AUX+
V_AUX-
|S₁₁₂₂|
R_DDC
PARAMETER
DDC mode passthrough voltage
I/O capacitance
On resistance AUX_SRCn to AUX_SNKn in DP
mode
On resistance SCL/SDA_DDC to AUX_SNK in
TMDS mode
On resistance AUX_SRC to AUX_SNK in TMDS
mode
On resistance variation with input signal voltage
change in DP mode
Differential input hysterisis
High-level input current
Low-level input current
Voltage on the Aux+ for PHY-CTS 3.19
Voltage on the Aux- for PHY-CTS 3.18
Differential line insertion loss
Switcheable pul-lup resistor on DDC at source
side (SCL_DDC, SDA_DDC)
TEST CONDITIONS
V_{CAD_SNK} = V_IH; I_O = 100 µA
V_IO = 0 V; f(test) = 1 MHz
V_CC = 3.0 V w/ V_I =2.85V or
V_CC = 3.6 V w/ V_I = 3.4 V; I_O = 5 mA
I_O = 3 mA
I_O = 3 mA
V_CC = 3.6 V, I_O = 5 mA, V_I = 2.6 to 3.4 V,
V_CC = 3.0 V, I_O = 5 mA, V_I = 0 to 0.4 V
By design (simulation only)
V_I = V_CC
V_I = GND; CAD_SNK = V_IH
V_I = GND; At DDC inputs
1M (5%) pullup to V_CC and 100kΩ pulldown to GND on
AUX+; V_CC = 3.3 V
100kΩ pullup to V_CC and 1M (5%) pulldown to GND on
AUX-;
V_CC = 3.3 V
V_ID = 400 mV, AC coupled; p-channel biasing 0.3 V and
n-channel 3.0V; 360 MHz sine wave; CAD_SNK=V_IL
CAD_SNK = V_IH
MIN TYP MAX UNIT
1.9
V
10
pF
5
10
Ω
15
30
Ω
10
20
Ω
5
Ω
50
mV
-5
5 µA
-5
5
µA
80
0
0.4
V
2.4
3.6
V
1.6
3 dB
48 60 72 kΩ
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): SN75DP130
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