SN75061 Datasheet, PDF (11/13 Pages) Texas Instruments – DRIVER/RECEIVER PAIR WITH SQUELCH

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SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
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SLLS026C − JANUARY 1987 − REVISED JULY 1990
PARAMETER MEASUREMENT INFORMATION
DLEN at 0.5 V
Generator
(see Note A)
5V
DRDLAJ
Rext = 62 kΩ
Cext = 100 pF
DRO +
DRI
50 Ω
DRO −
DATEN at 3 V
CL = 50 pF
(see Note B)
Output
RL = 100 Ω
TEST CIRCUIT
3V
Input
Output
tw(en)
2.3 V
0V
0.5 V
VOH
0V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 200 kHz, duty cycle ≤ 50%, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Test Circuit and Voltage Waveforms for Enable Pulse Duration With Delay Enable Low
5V
Generator
(see Note A) ^{50 Ω}
SQDLAJ
Rext = 51 kΩ
Cext = 50 pF
RXI +
1.5 V
RXI −
Open
SQTHAJ
SQRXO
RXO
SQDLI
Output
CL = 15 pF
(see Note B)
Input
Output
1.5 V 1.5 V
ten(RX)
1.3 V 1.3 V
3V
0V
VOH
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, duty cycle ≤ 50%, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Test Circuit and Voltage Waveforms for Receiver Enable (Unsquelch) Time
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