SN54ABT18245 Datasheet, PDF (11/30 Pages) Texas Instruments – SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS

SN54ABT18245
SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS
SGBS307A – AUGUST 1994 – REVISED JANUARY 1995
instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each
instruction.
Table 3. Instruction-Register Opcodes
BINARY CODE†
BIT 7 → BIT 0
MSB → LSB
SCOPE OPCODE
DESCRIPTION
SELECTED DATA
REGISTER
00000000
EXTEST
Boundary scan
Boundary scan
10000001
IDCODE
Identification read
Device identification
10000010
00000011
10000100
00000101
SAMPLE/PRELOAD
BYPASS‡
BYPASS‡
BYPASS‡
Sample boundary
Bypass scan
Bypass scan
Bypass scan
Boundary scan
Bypass
Bypass
Bypass
00000110
HIGHZ
Control boundary to high impedance
Bypass
10000111
10001000
CLAMP
BYPASS‡
Control boundary to 1/0
Bypass scan
Bypass
Bypass
00001001
RUNT
Boundary-run test
Bypass
00001010
READBN
Boundary read
Boundary scan
10001011
READBT
Boundary read
Boundary scan
00001100
CELLTST
Boundary self test
Boundary scan
10001101
TOPHIP
Boundary toggle outputs
Bypass
10001110
SCANCN
Boundary-control register scan
Boundary control
00001111
SCANCT
Boundary-control register scan
Boundary control
All others
BYPASS
Bypass scan
Bypass
† _{Bit 7 is used to maintain even parity in the 8-bit instruction.}
‡ _{The BYPASS instruction is executed in lieu of a SCOPE ™ instruction that is not supported in the ′ABT18245.}
MODE
Test
Normal
Normal
Normal
Normal
Normal
Modified test
Test
Normal
Test
Normal
Test
Normal
Test
Normal
Test
Normal
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST instruction. The BSR is selected in the
scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has
been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data scanned into
the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at the device I/O pins
is passed through the I/O BSCs to the normal on-chip logic. For I/O pins, the operation of a pin as input or output
is determined by the contents of the output-enable BSCs (bits 43 – 40 of the BSR). When a given output enable
is active (logic 1), the associated I/O pins operate in the output mode. Otherwise, the I/O pins operate in the input
mode. The device operates in the test mode.
identification read
This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the
scan path. The device operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured
in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs
associated with I/O pins in the output mode. The device operates in the normal mode.
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