OP07C Datasheet, PDF (11/21 Pages) STMicroelectronics – VERY LOW OFFSET SINGLE BIPOLAR OPERATIONAL AMPLIFIERS

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12 Layout
OP07C, OP07D
SLOS099G – OCTOBER 1983 – REVISED NOVEMBER 2014
12.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. On multilayer PCBs, one or more layers are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as
opposed to in parallel, with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
12.2 Layout Example
RIN
VIN
+
RG
RF
VOUT
Figure 7. Operational Amplifier Schematic for Noninverting Configuration
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RG
GND
RF
OFFSET N1
IN1í
OFFSET N2
VCC+
VS+
Use low-ESR, ceramic
bypass capacitor
VIN
Only needed for
dual-supply
operation
IN1+
RIN
VCCí
GND
VS-
(or GND for single supply)
VOUT
OUT
NC
GND
Ground (GND) plane on another layer
Figure 8. Operational Amplifier Board Layout for Noninverting Configuration
Copyright © 1983–2014, Texas Instruments Incorporated
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