LP2996-N_16 Datasheet, PDF (11/28 Pages) Texas Instruments – DDR Termination Regulator

LP2996-N
www.ti.com
SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013
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AIRFLOW (Linear Feet Per Minute)
Figure 23. θ_JA vs Airflow Speed (JEDEC Board with 4 Vias)
Optimizing the θ_JA and placing the LP2996-N in a section of a board exposed to lower ambient temperature
allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by
summing the three main sources of loss: output current at V_TT, either sinking or sourcing, and quiescent current
at AVIN and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation
can be calculated from the following equations:
P_D = P_AVIN + P_VDDQ + P_VTT
where
(3)
P_AVIN = I_AVIN * V_AVIN
(4)
P_VDDQ = V_VDDQ * I_VDDQ = V_VDDQ2 x R_VDDQ
(5)
To calculate the maximum power dissipation at V_TT both conditions at V_TT need to be examined, sinking and
sourcing current. Although only one equation will add into the total, V_TT cannot source and sink current
simultaneously.
P_VTT = V_VTT x I_LOAD (Sinking) or
(6)
P_VTT = ( V_PVIN - V_VTT) x I_LOAD (Sourcing
(7)
The power dissipation of the LP2996-N can also be calculated during the shutdown state. During this condition
the output V_TT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source
any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at
AVIN and the constant impedance that is seen at the VDDQ pin.
P_D = P_AVIN + P_VDDQ
P_AVIN = I_AVIN x V_AVIN
P_VDDQ = V_VDDQ * I_VDDQ = V_VDDQ2 x R_VDDQ
(8)
(9)
(10)
Typical Application Circuits
Several different application circuits have been shown in Figure 24 through Figure 33 to illustrate some of the
options that are possible in configuring the LP2996-N. Graphs of the individual circuit performance can be found
in the Typical Performance Characteristics section in the beginning of the datasheet. These curves illustrate how
the maximum output current is affected by changes in AVIN and PVIN.
SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL-2 termination scheme it is recommended to connect all
the input rails to the 2.5V rail. This provides an optimal trade-off between power dissipation and component count
and selection. An example of this circuit can be seen in Figure 24.
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