DLP6500FYE Datasheet, PDF (11/51 Pages) Texas Instruments – DMD

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DLP6500FYE
DLPS053A – OCTOBER 2014 – REVISED FEBRUARY 2016
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
SUPPLY VOLTAGES^{(1) (2)}
VCC
Supply voltage for LVCMOS core logic
VCCI
VOFFSET
Supply voltage for LVDS receivers
Supply voltage for HVCMOS and micromirror electrodes⁽²⁾
VBIAS
Supply voltage for micromirror electrodes
VRESET
Supply voltage for micromirror electrodes
|VCCI–VCC|
Supply voltage delta (absolute value) ⁽³⁾
|VBIAS–VOFFSET|
Supply voltage delta (absolute value)⁽⁴⁾
LVCMOS PINS
V_IH
V_IL
I_OH
I_OL
T_PWRDNZ
SCP INTERFACE⁽⁷⁾
High level Input voltage ⁽⁵⁾
Low level Input voltage⁽⁵⁾
High level output current at V_OH = 2.4 V
Low level output current at V_OL = 0.4 V
PWRDNZ pulse width⁽⁶⁾
ƒ_clock
t_{SCP_SKEW}
t_{SCP_DELAY}
t_{SCP_BYTE_INTERVAL}
t_{SCP_NEG_ENZ}
t_{SCP_PW_ENZ}
t_{SCP_OUT_EN}
ƒ_clock
SCP clock frequency⁽⁸⁾
Time between valid SCPDI and rising edge of SCPCLK⁽⁹⁾
Time between valid SCPDO and rising edge of SCPCLK⁽⁹⁾
Time between consecutive bytes
Time between falling edge of SCPENZ and the first rising edge of SCPCLK
SCPENZ inactive pulse width (high level)
Time required for SCP output buffer to recover after SCPENZ (from tri-state)
SCP circuit clock oscillator frequency ⁽¹⁰⁾
MIN NOM
MAX UNIT
3.15
3.3
3.15
3.3
8.25
8.5
15.5
16
–9.5
–10
3.45
V
3.45
V
8.75
V
16.5
V
–10.5
V
0.3
V
8.75
V
1.7
2.5 VCC + 0.15
V
– 0.3
0.7
V
–20
mA
15
mA
10
ns
–800
1
30
1
9.6
500
kHz
800
ns
700
ns
µs
ns
µs
1.5
ns
11.1
MHz
(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(4) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply
Recommendations for additional information.
(5) Tester Conditions for V_IH and V_IL:
Frequency = 60MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)
Frequency = 60MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)
(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the
SCPDO output pin.
(7) For all Serial Communications Port (SCP) operations, DCLK_A and DCLK_B are required.
(8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(9) Refer to Figure 3.
(10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
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