CDCVF857_17 Datasheet, PDF (11/23 Pages) Texas Instruments – 2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

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CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
80%
80%
V_OH, V_IH
Clock Inputs
and Outputs
20%
t_r
20%
V_OL, V_IL
t_f
V_80% – V_20%
t_slr(I/O) =
t_r
V_80% – V_20%
t_slf(I/O) =
t_f
Figure 9. Input and Output Slew Rates
T0179-01
Card
Via
V_DDQ
Bead⁽²⁾
0603
AV_DD
4.7 mF
1206
0.1 mF
0603
2200 pF⁽¹⁾
0603
PLL
GND
Card
Via
AGND
S0232-01
(1) Place the 2200-pF capacitor close to the PLL.
(2) Recommended bead: Fair-Rite P/N 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz).
NOTE: Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect
trace to one GND via (farthest from the PLL).
Figure 10. Recommended AV_DD Filtering
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