CDCE937-Q1_15 Datasheet, PDF (11/30 Pages) Texas Instruments – PROGRAMMABLE 3-PLL VCXO CLOCK SYNTHESIZER

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CDCE937-Q1
CDCEL937-Q1
SCAS892B – FEBRUARY 2010 – REVISED MAY 2010
S1/SDA and S2/SCL pins of the CDCE937/CDCEL937 are dual function pins. In default configuration they are
defined as SDA/SCL for the serial interface. They can be programmed as control-pins (S1/S2) by setting the
relevant bits in the EEPROM. Note that the changes to the Control register (Bit [6] of Byte [02]) have no effect
until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if V_DDOUT is
forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi-use pin, it is a control pin only.
DEFAULT DEVICE SETTING
The internal EEPROM of CDCE937/CDCEL937 is preconfigured as shown in Figure 6. (The input frequency is
passed through to the output as a default). This allows the device to operate in default mode without the extra
production step of program it. The default setting appears after power is supplied or after power-down/up
sequence until it is re-programmed by the user to a different application configuration. A new register setting is
programmed via the serial SDA/SCL Interface.
V_DD
GND
Vddout
Xin
27 MHz
Crystal
Xout
“1” = outputs enabled
“0” = outputs 3-State
Programming Bus
S0
SDA
SCL
X-tal
EEPROM
Programming
and
SDA/SCA
Register
Input Clock
PLL 1
power down
PLL Bypass
PLL 2
power down
PLL Bypass
Pdiv1 =1
Pdiv2 = 1
Pdiv3 = 1
Pdiv4 = 1
Pdiv5 = 1
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
Y1 = 27MHz
Y2 = 27 MHz
Y3 = 27 MHz
Y4 = 27 MHz
Y5 = 27 MHz
PLL 3
power down
PLL Bypass
Pdiv6 = 1
Pdiv7 = 1
LV
CMOS
LV
CMOS
Y6 = 27 MHz
Y7 = 27 MHz
Figure 6. Default Device Setting
Table 4 shows the factory default setting for the Control Terminal Register (external control pins). In normal
operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1)
can be selected with S0, as S1 and S2 configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register⁽¹⁾
External Control Pins
S2
S1
S0
SCL (I2C) SDA (I2C) 0
SCL (I2C) SDA (I2C) 1
Y1
Output
Selection
Y1
3-state
enabled
PLL1 Settings
PLL2 Settings
PLL3 Settings
Frequency
Selection
SSC
Selection
Output
Selection
Frequenc
y
Selection
SSC
Selection
Output
Selection
Frequenc
y
Selection
SSC
Selection
Output
Selection
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
f_{VCO1_0}
f_{VCO1_0}
off
3-state
f_{VCO2_0}
off
3-state
f_{VCO1_0}
off
3-state
off
enabled
f_{VCO2_0}
off
enabled
f_{VCO1_0}
off
enabled
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode
switches all outputs ON or OFF (as previously predefined).
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE937-Q1
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