ADC08500_14 Datasheet, PDF (11/46 Pages) Texas Instruments – ADC08500 High Performance, Low Power 8-Bit, 500 MSPS A/D Converter

ADC08500
www.ti.com
SNAS373E – MAY 2007 – REVISED APRIL 2013
Converter Electrical Characteristics (continued)
The following specifications apply after calibration for V_A = V_DR = +1.9V_DC, OutV = 1.9V, V_IN FSR (a.c. coupled) = differential
870 mV_P-P, C_L = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f_CLK = 500 MHz at 0.5V_P-P with 50% duty cycle,
V_BG = Floating, Non-Extended Control Mode, SDR Mode, R_EXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for T_A = T_MIN to T_MAX. All other limits T_A = 25°C, unless otherwise noted. See ⁽¹⁾⁽²⁾
Symbol
Parameter
Conditions
Typical ⁽³⁾ Limits ⁽³⁾
Units
(Limits)
CHANNEL-TO-CHANNEL CHARACTERISTICS
Offset Error Match
1
LSB
Positive Full-Scale Error Match
Zero offset selected in Control Register
1
LSB
Negative Full-Scale Error Match
Zero offset selected in Control Register
1
LSB
Phase Matching (I, Q)
CLOCK INPUT CHARACTERISTICS
F_IN = 1.0 GHz
<1
Degree
V_ID
Differential Clock Input Level
I_I
Input Current
C_IN
Input Capacitance ⁽⁷⁾⁽⁸⁾
Sine Wave Clock
Square Wave Clock
V_IN = 0 or V_IN = V_A
Differential
Each input to ground
0.6
0.6
±1
0.02
1.5
0.4
V_P-P (min)
2.0
V_P-P (max)
0.4
V_P-P (min)
2.0
V_P-P (max)
µA
pF
pF
DIGITAL CONTROL PIN CHARACTERISTICS
V_IH
Logic High Input Voltage
V_IL
Logic Low Input Voltage
C_IN
Input Capacitance ^(8)(10)
DIGITAL OUTPUT CHARACTERISTICS
See ⁽⁹⁾
See ⁽⁹⁾
Each input to ground
0.85 x V_A
V (min)
0.15 x V_A
V (max)
1.2
pF
V_OD
LVDS Differential Output Voltage
Δ V_{O DIFF}
Change in LVDS Output Swing
Between Logic Levels
Measured differentially, OutV = V_A, V_BG
= Floating, ⁽¹¹⁾
710
Measured differentially, OutV = GND,
V_BG = Floating, ⁽¹¹⁾
510
±1
400
mV_P-P (min)
920
mV_P-P (max)
280
mV_P-P (min)
720
mV_P-P (max)
mV
V_OS
V_OS
Δ V_OS
Output Offset Voltage, see Figure 3
Output Offset Voltage, see Figure 3
V_BG = Floating
V_BG = V_A ⁽¹¹⁾
Output Offset Voltage Change Between
Logic Levels
800
mV
1200
mV
±1
mV
I_OS
Output Short Circuit Current
Z_O
Differential Output Impedance
V_OH
Cal_Run High level output
V_OL
Cal_Run Low level output
POWER SUPPLY CHARACTERISTICS
Output+ & Output- connected to 0.8V
±4
I_OH = -400 uA ⁽⁹⁾
I_OH = 400 uA ⁽⁹⁾
100
1.65
1.5
0.15
0.3
mA
Ohms
V
V
I_A
Analog Supply Current
PD = Low
PD = High
340
408
mA (max)
1.8
mA
I_DR
Output Driver Supply Current
PD = Low
PD = High
112
157
mA (max)
0.012
mA
(7) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
(8) This parameter is specified by design and is not tested in production.
(9) This parameter is specified by design and/or characterization and is not tested in production.
(10) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated
from the die capacitances by lead and bond wire inductances.
(11) Tying V_BG to the supply rail will increase the output offset voltage (V_OS) by 400 mV (typical), as shown in the V_OS specification above.
Tying V_BG to the supply rail will also affect the differential LVDS output voltage (V_OD), causing it to increase by 40mV (typical).
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