74SSTUB32865A Datasheet, PDF (11/21 Pages) Texas Instruments – 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

74SSTUB32865A
www.ti.com
SLAS562 – NOVEMBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) ⁽¹⁾
V_CC Supply voltage range
V_I
Input voltage range ^{(2) (3)}
V_O Output voltage range ^{(2) (3)}
I_IK Input clamp curren t(V_I < 0 or V_I > V_CC)
I_OK Output clamp current (V_O < 0 or V_O > V_CC)
I_O Continuous output current (V_O = 0 to V_CC)
I_CC Continuous current through each V_CC or GND
θ_JA Thermal resistance, junction to ambient⁽⁴⁾
θ_JC Thermal resistance, junction to case⁽⁴⁾
T_stg Storage temperature range
No Airflow
Airflow 200 ft/min
No Airflow
VALUE
–0.5 to 2.5
–0.5 to V_CC + 0.5
–0.5 to V_CC + 0.5
±50
±50
±50
±100
51.2
47.2
29.7
–65 to 150
UNIT
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 2.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS⁽¹⁾
V_CC
V_REF
V_TT
V_I
V_IH
V_IL
V_IH
V_IL
V_IH
V_IL
V_ICR
V_I(PP)
I_OH
Supply voltage
Reference voltage
Termination voltage
Input voltage
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
I_OL
Low-level output current
T_A
Operating free-air temperature
Data inputs, DCSn, PARIN
Data inputs, DCSn, PARIN
Data inputs, DCSn, PARIN
Data inputs, DCSn, PARIN
RESET, CSGateEN, C
RESET, CSGateEN, C
CK, CK
CK, CK
Q outputs
Q outputs
PTYERR output
MIN
1.7
0.49 × V_CC
V_REF–40 mV
0
V_REF+250 mV
V_REF+125 mV
0.65 × V_CC
0.675
600
30
-40
NOM
0.5 × V_CC
V_REF
MAX
1.9
0.51 × V_CC
V_REF+40mV
V_CC
V_REF–250 mV
V_REF–125 mV
0.35 × V_CC
1.125
–12
12
UNIT
V
V
V
V
V
V
V
V
V
V
V
mV
mA
mA
85 °C
(1) The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS
Inputs (SCBA004).
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
V_OH Q outputs
I_OH = –100 µA
I_OH = –8 mA
TEST CONDITIONS
V_CC
1.7 V to 1.9 V
1.7 V
MIN
V_CC –0.2
1.2
TYP ⁽¹⁾
MAX
UNIT
V
(1) All typical values are at V_CC = 1.8 V, T_A = 25°C.
Copyright © 2007, Texas Instruments Incorporated
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