TMS320C6413_12 Datasheet, PDF (107/146 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

Programmable Synchronous Interface Timing
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
AARE/ASDCAS/ASADS/ASRE§
1
1
2
3
BE1
BE2
BE3
BE4
4
5
EA1
EA2
EA3
EA4
10
10
11
Q1
Q2
Q3
Q4
8
8
AAOE/ASDRAS/ASOE§
12
12
AAWE/ASDWE/ASWE§
† _{The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space}
Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0.
‡ _{The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):}
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
§ _{AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,}
respectively, during programmable synchronous interface accesses.
Figure 7−10. Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 0)^{†‡§}
April 2004 − Revised January 2006
SPRS247F ¹⁰⁷