LM3S9U81 Datasheet, PDF (1057/1277 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S9U81 Microcontroller
OTG A /
Host
Register 165: USB Transmit Control and Status Endpoint 1 High
(USBTXCSRH1), offset 0x113
Register 166: USB Transmit Control and Status Endpoint 2 High
(USBTXCSRH2), offset 0x123
Register 167: USB Transmit Control and Status Endpoint 3 High
(USBTXCSRH3), offset 0x133
Register 168: USB Transmit Control and Status Endpoint 4 High
(USBTXCSRH4), offset 0x143
Register 169: USB Transmit Control and Status Endpoint 5 High
(USBTXCSRH5), offset 0x153
Register 170: USB Transmit Control and Status Endpoint 6 High
(USBTXCSRH6), offset 0x163
Register 171: USB Transmit Control and Status Endpoint 7 High
(USBTXCSRH7), offset 0x173
Register 172: USB Transmit Control and Status Endpoint 8 High
(USBTXCSRH8), offset 0x183
Register 173: USB Transmit Control and Status Endpoint 9 High
(USBTXCSRH9), offset 0x193
Register 174: USB Transmit Control and Status Endpoint 10 High
(USBTXCSRH10), offset 0x1A3
Register 175: USB Transmit Control and Status Endpoint 11 High
(USBTXCSRH11), offset 0x1B3
Register 176: USB Transmit Control and Status Endpoint 12 High
(USBTXCSRH12), offset 0x1C3
Register 177: USB Transmit Control and Status Endpoint 13 High
(USBTXCSRH13), offset 0x1D3
Register 178: USB Transmit Control and Status Endpoint 14 High
(USBTXCSRH14), offset 0x1E3
Register 179: USB Transmit Control and Status Endpoint 15 High
(USBTXCSRH15), offset 0x1F3
USBTXCSRHn is an 8-bit register that provides additional control for transfers through the currently
selected transmit endpoint.
OTG B /
Device
January 23, 2012
Texas Instruments-Production Data
1057