LM3S5656 Datasheet, PDF (1053/1140 Pages) Texas Instruments – Stellaris® LM3S5656 Microcontroller

Stellaris^® LM3S5656 Microcontroller
Table 22-3. Signals by Signal Name (continued)
Pin Name
U2Rx
U2Tx
USB0DM
Pin Number Pin Mux / Pin
Assignment
58
PB4 (4)
61
PD0 (4)
8
PE4 (5)
62
PD1 (4)
45
fixed
Pin Type
I
O
I/O
USB0DP
46
fixed
I/O
USB0EPEN
USB0ID
14
PC5 (6)
O
25
PA6 (8)
47
PB2 (8)
41
PB0
I
USB0PFLT
USB0RBIAS
USB0VBUS
VBAT
VDD
VDDA
6
PE0 (9)
I
15
PC6 (7)
16
PC7 (6)
26
PA7 (8)
27
PB3 (8)
48
fixed
O
42
PB1
I/O
37
fixed
-
12
fixed
-
28
43
59
3
fixed
-
VDDC
9
fixed
-
23
38
54
Buffer Type^a Description
TTL
TTL
Analog
Analog
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
Bidirectional differential data pin (D- per USB
specification) for USB0.
Bidirectional differential data pin (D+ per USB
specification) for USB0.
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
Analog
TTL
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
Analog
Analog
Power
Power
9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
Positive supply for I/O and some logic.
Power
Power
The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 24-2 on page 1066, regardless
of system implementation.
Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.3 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to the LDO pin and an external capacitor
as specified in Table 24-6 on page 1071.
January 21, 2012
Texas Instruments-Production Data
1053