TMS320F28335_16 Datasheet, PDF (100/199 Pages) Texas Instruments – PRODUCTION DATA information is current as of publication date

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M – JUNE 2007 – REVISED AUGUST 2012
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
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GPIOLMPSEL
LPMCR0
Low-Power
Modes Block
GPIOXINT7SEL
GPIOXNMISEL
External Interrupt
MUX
PIE
Asynchronous
path
GPxPUD
Internal
Pullup
GPxQSEL1/2
GPxCTRL
Input
Qualification
GPIOx pin
Asynchronous path
High-Impedance
Output Control
0 = Input, 1 = Output
XRS
GPxDAT (read)
00
N/C
01
Peripheral 1 Input
10
Peripheral 2 Input
11
Peripheral 3 Input
GPxTOGGLE
GPxCLEAR
GPxSET
00
GPxDAT (latch)
01
Peripheral 1 Output
10
Peripheral 2 Output
11
Peripheral 3 Output
00
GPxDIR (latch)
01
Peripheral 1 Output Enable
10
Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the
TMS320x2833x, 2823x System Control and Interrupts Reference Guide (literature number SPRUFB0 ) for pin-specific
variations.
Figure 4-18. GPIO MUX Block Diagram
100 Peripherals
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TMS320F28232