TMS320C6727B_17 Datasheet, PDF (100/119 Pages) Texas Instruments – Floating-Point Digital Signal Processors

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008
www.ti.com
The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A
followed by 0xA35C in two separate writes) must be continually written to the key register before the
watchdog counter counts down to zero; otherwise, the DSP will be reset. This feature can be used to
provide an added measure of robustness against a software failure. If the application fails and ceases to
write to the watchdog key; the watchdog will respond by resetting the DSP and thereby restarting the
application.
Note that Counter 0 and Compare 0 are used by DSP BIOS to generate the tick counter it requires;
however, Capture 0 is still available for use by the application as well as the remaining RTI resources.
4.16.2 RTI/Digital Watchdog Registers Description(s)
Table 4-38 is a list of the RTI registers.
BYTE ADDRESS
0x4000 0014
0x4200 0000
0x4200 0004
0x4200 0008
0x4200 000C
0x4200 0010
0x4200 0014
0x4200 0018
0x4200 0020
0x4200 0024
0x4200 0030
0x4200 0034
0x4200 0038
0x4200 0040
0x4200 0044
0x4200 0050
0x4200 0054
0x4200 0058
0x4200 005C
0x4200 0060
0x4200 0064
0x4200 0068
0x4200 006C
0x4200 0070
0x4200 0074
0x4200 0080
0x4200 0084
0x4200 0088
Table 4-38. RTI Registers
REGISTER NAME
DESCRIPTION
Device-Level Configuration Registers Controlling RTI
CFGRTI
Selects the sources for the RTI input captures from among the six McASP DMA event.
RTI Internal Registers
RTIGCTRL
Global Control Register. Starts / stops the counters.
Reserved
Reserved bit.
RTICAPCTRL
Capture Control. Controls the capture source for the counters.
RTICOMPCTRL
Compare Control. Controls the source for the compare registers.
RTIFRC0
Free-Running Counter 0. Current value of free-running counter 0.
RTIUC0
Up-Counter 0. Current value of prescale counter 0.
RTICPUC0
Compare Up-Counter 0. Compare value compared with prescale counter 0.
RTICAFRC0
Capture Free-Running Counter 0. Current value of free-running counter 0 on external
event.
RTICAUC0
Capture Up-Counter 0. Current value of prescale counter 0 on external event.
RTIFRC1
Free-Running Counter 1. Current value of free-running counter 1.
RTIUC1
Up-Counter 1. Current value of prescale counter 1.
RTICPUC1
Compare Up-Counter 1. Compare value compared with prescale counter 1.
RTICAFRC1
Capture Free-Running Counter 1. Current value of free-running counter 1 on external
event.
RTICAUC1
Capture Up-Counter 1. Current value of prescale counter 1 on external event.
RTICOMP0
Compare 0. Compare value to be compared with the counters.
RTIUDCP0
Update Compare 0. Value to be added to the compare register 0 value on compare
match.
RTICOMP1
Compare 1. Compare value to be compared with the counters.
RTIUDCP1
Update Compare 1. Value to be added to the compare register 1 value on compare
match.
RTICOMP2
Compare 2. Compare value to be compared with the counters.
RTIUDCP2
Update Compare 2. Value to be added to the compare register 2 value on compare
match.
RTICOMP3
Compare 3. Compare value to be compared with the counters.
RTIUDCP3
Update Compare 3. Value to be added to the compare register 3 value on compare
match.
Reserved
Reserved bit.
Reserved
Reserved bit.
RTISETINT
Set Interrupt Enable. Sets interrupt enable bits int RTIINTCTRL without having to do a
read-modify-write operation.
RTICLEARINT
Clear Interrupt Enable. Clears interrupt enable bits int RTIINTCTRL without having to
do a read-modify-write operation.
RTIINTFLAG
Interrupt Flags. Interrupt pending bits.
100 Peripheral and Electrical Specifications
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