TPS2388 Datasheet, PDF (10/82 Pages) Texas Instruments – IEEE 802.3at 8-Channel Power-over-Ethernet PSE Controller

TPS2388
SLUSC25A – FEBRUARY 2015 – REVISED AUGUST 2017
6.6 Timing Requirements
f_SCL
t_LOW
t_HIGH
t_fo
C_I2C
C_{I2C_SDA}
t_SU,DATW
t_SU,DATR
t_HD,DATW
t_HD,DATR
t_fSDA
t_rSDA
t_r
t_f
t_BUF
t_HD,STA
t_SU,STA
t_SU,STO
t_{FLT_INT}
t_DG
t_RDG
t_{bit_OSS}
t_{OSS_IDL}
t_{r_OSS}
t_{f_OSS}
t_{WDT_I2C}
SCL clock frequency
LOW period of the clock
HIGH period of the clock
SDAO output fall time
SDAO, 2.3 → 0.8 V, Cb = 10 pF,
10 kΩ pull-up to 3.3 V
SDAO, 2.3 → 0.8 V, Cb = 400 pF,
1.3 kΩ pull-up to 3.3 V
SCL capacitance
SDAI, SDAO capacitance (each)
Data set-up time (Write operation)
Data set-up time (Read operation)
SDAO, Cb = 10 pF,
1.3 kΩ pull-up to 3.3V
Data hold time (Write operation)
Data hold time (Read operation)
Input fall times of SDAI
2.3 → 0.8 V
Input rise times of SDAI
0.8 → 2.3 V
Input rise time of SCL
0.8 → 2.3 V
Input fall time of SCL
2.3 → 0.8 V
Bus free time between a STOP and START condition
Hold time after (repeated) Start condition
Repeated Start condition set-up time
Stop condition set-up time
Fault to INT assertion
Time to internally register an Interrupt fault,
from port turn off
Suppressed spike pulse width, SDAI and SCL
RESET input minimum pulse width (deglitch time)
3-bit OSS bit period
MbitPrty = 1
Idle time between consecutive shutdown
code transmission in 3-bit mode
MbitPrty = 1
Input rise time of OSS in 3-bit mode
0.8 → 2.3 V, MbitPrty = 1
Input fall time of OSS in 3-bit mode
I²C Watchdog trip delay
2.3 → 0.8 V, MbitPrty = 1
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MIN TYP
10
1.3
0.6
21
MAX
400
UNIT
kHz
µs
µs
250 ns
21
100
600
0
150
20
20
20
20
1.3
0.6
0.6
0.6
50
50
24
25
48
50
1
1
1.1 2.2
250 ns
10 pF
6 pF
ns
ns
ns
600 ns
250 ns
300 ns
300 ns
200 ns
µs
µs
µs
µs
500 µs
ns
5 µs
26 µs
µs
300 ns
300 ns
3.3 s
10
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