TLV320DAC3101 Datasheet, PDF (10/100 Pages) Texas Instruments – Low-Power Stereo Audio DAC With Audio Processing and Stereo Class-D Speaker Amplifier

TLV320DAC3101
SLAS666A – JANUARY 2010 – REVISED MAY 2012
3.4.2 I²S/LJF/RJF Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization only.
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WCLK
BCLK
DIN
t_H(BCLK)
t_L(BCLK)
t_s(WS)
t_h(WS)
t_s(DI)
t_h(DI)
t_r
t_f
t_H(BCLK)
t_h(WS)
t_r
t_S(WS)
t_L(BCLK)
t_S(DI)
t_f
t_h(DI)
PARAMETER
BCLK high period
BCLK low period
WCLK setup
WCLK hold
DIN setup
DIN hold
Rise time
Fall time
IOVDD = 1.1 V
MIN MAX
35
35
8
8
8
8
4
4
IOVDD = 3.3 V
MIN MAX
35
35
6
6
6
6
4
4
Figure 3-2. I²S/LJF/RJF Timing in Slave Mode
T0145-11
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
10
ELECTRICAL SPECIFICATIONS
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