TIC12400-Q1 Datasheet, PDF (10/127 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) With Integrated ADC and Adjustable Wetting Current for Automotive Systems

TIC12400-Q1
SCPS260 – AUGUST 2017
www.ti.com
6.6 Timing Requirements
V_S= 4.5 V to 35 V, V_DD= 3 V to 5.5 V, and 10 pF capacitive load on SO unless otherwise noted; verified by design and
characterization
PARAMETER
TEST CONDITION
MIN NOM MAX UNIT
SWITCH MONITORING, INTERRUPT, STARTUP AND RESET
t_{POLL_ACT}
t_{POLL_ACT}
_M
t_POLL
t_COMP
Polling active time accuracy
Polling active time accuracy for matrix inputs
Polling time accuracy
Comparator detection time
t_ADC
ADC Conversion time
Polling mode
Polling mode with matrix
enabled
Polling mode
Sample and hold time
included
-12%
-12%
-12%
12%
12%
12%
18
µs
24
µs
t_{CCP_TRAN}
Transition time between last input sampling and start of
clean current
20
µs
t_{CCP_ACT}
t_STARTUP
t_{INT_ACTIV}
E
t_{INT_INACT}
IVE
t_{INT_IDLE}
t_RESET
Clean current active time
Polling startup time
Active INT assertion duration
INT de-assertion duration during a pending interrupt
Interrupt idle time
Time required to keep the RESET pin high to successfully
reset the device (no pending interrupt)⁽¹⁾
-12%
200
1.5
3
80
2
12%
300
400 µs
2
2.5 ms
4
5 ms
100
120 µs
µs
t_REACT
Delay between a fault event (OV, UV, TW, or TSD) to a
high to low transition on the INT pin
See Figure 13 for OV
example.
20 µs
SPI INTERFACE
t_LEAD
Falling edge of CS to rising edge of SCLK setup time
100
t_LAG
Falling edge of SCLK to rising edge of CS setup time
100
t_SU
SI to SCLK falling edge setup time
30
t_HOLD
SI hold time after falling edge of SCLK
20
t_VALID
Time from rising edge of SCLK to valid SO data
t_SO(EN) Time from falling edge of CS to SO low-impedance
t_SO(DIS) Time from rising edge of CS to SO high-impedance
Loading of 1 kΩ to GND.
See Figure 14.
ns
ns
ns
ns
70 ns
60 ns
60 ns
t_R
t_F
t_{INTER_FR}
AME
t_CKH
t_CKL
t_INITIATION
SI, CS, and SCLK signals rise time
SI, CS, and SCLK signals fall time
Delay between two SPI communication (CS low)
sequences
SCLK High time
SCLK Low time
Delay between valid V_DD voltage and initial SPI
communication
5
30 ns
5
30 ns
1.5
µs
120
ns
120
ns
45
µs
(1) If there is a pending interrupt (/INT pin asserted low), it can take up to 1ms for the device to complete the reset.
10
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