TCM320AC56 Datasheet, PDF (10/23 Pages) Texas Instruments – VOICE-BAND AUDIO PROCESSORS (VBAP)

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAP)
SLWS016A – JUNE 1996 – REVISED APRIL 1997
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Figure 1 through Figure 4)
MIN NOM^† MAX UNIT
tt
Transition time, CLK and DCLKX /DCLKR
Duty cycle, CLK
10 ns
45% 50% 55%
Duty cycle, DCLKX /DCLKR
45% 50% 55%
† _{All nominal values are at VCC = 5 V, TA = 25°C.}
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
tsu(FSX)
th(FSX)
Setup time, FSX high before CLK↓
Hold time, FSX high after CLK↓
MIN MAX UNIT
20 468 ns
20 468 ns
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)
tsu(FSR)
th(FSR)
tsu(DIN)
th(DIN)
Setup time, FSR high before CLK↓
Hold time, FSR high after CLK↓
Setup time, DIN high or low before CLK↓
Hold time, DIN high or low after CLK↓
MIN MAX UNIT
20 468 ns
20 468 ns
20
ns
20
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
tsu(FSX)
th(FSX)
Setup time, FSX high before DCLKX↓
Hold time, FSX high after DCLKX↓
MIN
MAX
40 tc(DCLKX)– 40
35 tc(DCLKX)–35
UNIT
ns
ns
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
tsu(FSR)
th(FSR)
tsu(DIN)
th(DIN)
Setup time, FSR high before DCLKR↓
Hold time, FSR high after DCLKR↓
Setup time, DIN high or low before DCLKR↓
Hold time, DIN high or low after DCLKR↓
MIN
MAX
40
35 tc(DCLKR)–35
30
30
UNIT
ns
ns
ns
ns
switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
C_L = 0 to 10 pF (see Figure 2)
PARAMETER
TEST CONDITIONS MIN MAX UNIT
tpd1 From CLK bit 1 high to DOUT bit 1 valid
tpd2 From CLK high to DOUT valid, bits 2 to n
tpd3 From CLK bit n low to DOUT bit n Hi-Z
tpd4 From CLK bit 1 high to TSX active (low)
tpd5 From CLK bit n low to TSX inactive (high)
Rpullup = 1.24 kW
Rpullup = 1.24 kΩ
35 ns
35 ns
30
ns
40 ns
30
ns
10
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