TAS5086_17 Datasheet, PDF (10/49 Pages) Texas Instruments – PurePath Digital AUDIO SIX-CHANNEL PWM PROCESSOR

TAS5086
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
DETAILED DESCRIPTION
POWER SUPPLY
The TAS5086 power-supply section contains regulators that provide analog and digital regulated power for
various sections of the TAS5086. The analog supply supports the analog PLL while digital supplies support the
digital PLL, the digital audio processor, the pulse width modulator, and the output control (reclocker). The
power-supply section is enabled via VREG_EN.
CLOCK, ERROR RATE DETECTION, AND PLL
This module provides the timing and serial data interface for the TAS5086.
The TAS5086 is a clock slave device. It accepts MCLK, SCLK, and LRCLK.
The TAS5086 supports 64-f_S MCLK for the 176.4-kHz and 192-kHz data rates.
The TAS5086 accepts a 64-f_S SCLK rate for all MCLK ratios and a 48-f_S SCLK rate for MCLK ratios of 192 f_S
and 384 f_S.
TAS5086 checks to verify that SCLK is a specific value of 64 f_S or 48 f_S.
The TAS5086 supports a 1-f_S LRCLK.
The timing relationship of these clocks to SDIN[1:4] and SDOUT is shown in subsequent sections.
The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce a
196-MHz PLL output.
The TAS5086 can auto-detect and set the internal clock control logic to the appropriate settings for the
frequencies of 32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed
(176.4 kHz or 192 kHz). The automatic sample rate detection can be disabled and the values set via I²C.
The TAS5086 also supports an AM interference-avoidance mode during which the clock rate is adjusted, in
concert with the PWM sample rate converter, to produce a PWM output at 7-f_S, 8-f_S, or 9-f_S.
The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled.
The TAS5086 uses an internal oscillator time base to provide reference timing information for the following
functions:
• MCLK, SCLK, and LRCLK error detection
• I²C communication when power is first applied to the device
• Automatic data-rate detection and setting (32 kHz, normal, double, and quad speed)
• Automatic MCLK rate detection and setting (64, 128, 192, 256, 384, and 512 f_S)
OSCILLATOR TRIM
The TAS5086 PWM processor contains an internal oscillator for PLL reference. This reduces system cost
because an external reference is not required. After each power up or reset, a oscillator trim is needed; see the
Oscillator Trim Register (0x1B) section for a detailed procedure.
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