LP38856_14 Datasheet, PDF (10/20 Pages) Texas Instruments – 3A Fast-Response High-Accuracy LDO Linear Regulator with Enable

LP38856
SNVS336D – JUNE 2006 – REVISED OCTOBER 2011
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Bias Capacitor
The capacitor on the bias pin must be at least 1 µF. It can be any good quality capacitor (ceramic is
recommended).
INPUT VOLTAGE
The input voltage (V_IN) is the high current external voltage rail that will be regulated down to a lower voltage,
which is applied to the load. The input voltage must be at least V_OUT + V_DO, and no higher than whatever value is
used for V_BIAS.
BIAS VOLTAGE
The bias voltage (V_BIAS) is a low current external voltage rail required to bias the control circuitry and provide
gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3.0V to 5.5V to ensure proper
operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.
As the bias voltage rises above the UVLO threshold the device control circuitry become active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the
device will be functional, but the operating parameters will not be within the specified limits.
SUPPLY SEQUENCING
There is no requirement for the order that V_IN or V_BIAS are applied or removed. However, the output voltage
cannot be specified until both V_IN and V_BIAS are within the range of specified operating values.
If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be
diode clamped to ground. A Schottky diode is recommend for this diode clamp.
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when V_IN is abruptly taken low and C_OUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass
element is not driven, there will not be any reverse current flow through the pass element during a reverse
voltage event. The gate of the pass element is not driven when V_BIAS is below the UVLO threshold.
When V_BIAS is above the UVLO threshold the control circuitry is active and will attempt to regulate the output
voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass
element to the full V_BIAS potential when the output voltage begins to fall. In this condition, reverse current will flow
from the output pin to the input pin, limited only by the R_DS(ON) of the pass element and the output to input
voltage differential. This condition is outside the specified operating range and should be avoided.
ENABLE OPERATION
The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has
an internal pull-up, through a typical 180 kΩ resistor, to V_BIAS.
If the Enable pin is actively driven, pulling the Enable pin above the V_EN threshold of 1.25V (typical) will turn the
regulator output on, while pulling the Enable pin below the V_EN threshold will turn the regulator output off. There
is approximately 100 mV of hysteresis built into the Enable threshold provide noise immunity.
If the Enable function is not needed this pin should be left open, or connected directly to V_BIAS. If the Enable pin
is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while
the stray capacitance is charged through the internal resistance (r_EN).
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